Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 137UG074 (v2.2) February 22, 20101000BASE-X PCS/PMARShimBecause of small differences in the way the Virtex-II Pro and Virtex-4 FPGA RocketIOtransceivers output the clock correction status and data when RXNOTINTABLE isasserted, a shim is needed to modify the received data from the Virtex-4 FPGA RocketIOtransceiver (GT11) to the format that the EMAC is expecting. Table 4-9 shows the ports ofthis shim created by the CORE Generator tool for the SGMII and 1000BASE-X designs.1000BASE-X PCS/PMA Clock Management8-Bit Data ClientFigure 4-27 shows the clock management used with the 1000BASE-X PCS/PMA interfaceand an 8-bit data client. At a line rate of 1.25 Gb/s or below, oversampling is used by thebuilt-in MGT digital receiver to recover clock and data. See Chapter 3 of UG076, Virtex-4RocketIO Multi-Gigabit Transceiver User Guide for more details about the digital receiveroversampling operation. The inputs of the GT11CLK_MGT primitive are connected to anexternal, high-quality reference clock with a frequency of 250 MHz specifically for theMGT. The output SYNCLKOUT connects to the PLL reference clock input REFCLK.TXOUTCLK1, derived from the transmitter PLL, reflects the reference clock and drives theother clock inputs. It connects through a global buffer to PHYEMAC#GTXCLK and intoTXUSRCLK2 and RXUSRCLK2. TXUSRCLK and RXUSRCLK are not used and are tied toground.To ensure that the Ethernet MAC does not operate until the MGT has achieved allnecessary locks, the CLIENTEMAC#DCMLOCKED input signal to the EMAC# block isgenerated using the TXLOCK and RXLOCK signals from the MGT, and the DCMLOCKED output. Refer to the CORE Generator Ethernet MAC wrapper for the actualimplementation of this combined lock signal.The EMAC#CLIENTTXCLIENTCLKOUT output port must be connected to a BUFG todrive the transmit client logic in the FPGA fabric, and then is routed back into the inputport CLIENTEMAC#TXCLIENTCLKIN. This method is also used for the receive clientlogic.Table 4-9: Shim Port NamesPort Name I/O Width Descriptionrxusrclk2 I 1 Logic Clock.Rxstatus I 6 Status from GT11.Rxnotintable I 1 Status from GT11.rxd_in I 8 Data from GT11.rxcharisk_in I 1 Control from GT11.rxrundisp_in I 1 Status from GT11.Rxclkcorcnt O 3 Status in GT format.rxd_out O 8 Data in GT format when rxnotintableasserted.rxcharisk_out O 1 Control in GT/GT11 format.rxrundisp_out O 1 Control in GT/GT11 format.www.BDTIC.com/XILINX