Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 169UG074 (v2.2) February 22, 2010RAppendix AEthernet MAC Timing ModelThis appendix explains the timing parameters associated with the Ethernet MAC block. Itis intended to be used in conjunction with the Timing Analyzer (TRCE) report fromXilinx® software.Many signals enter and exit the Ethernet MAC block (as shown in Figure 2-3, page 21). Themodel presented in this appendix treats the Ethernet MAC block as a “black box.”Propagation delays internal to the Ethernet MAC block logic are ignored. Signals arecharacterized with setup and hold times for inputs, and with clock to valid output timesfor outputs.There are seven clocks associated with the Ethernet MAC block. Table 2-4, page 25 brieflydescribes the clock signals necessary to drive the Virtex®-4 FPGA Embedded Tri-ModeEthernet MAC.Timing ParametersParameter designations are constructed to reflect the functions they perform as well as theI/O signals to which they are synchronous. The following subsections explain the meaningof each of the basic timing parameter designations used in Table A-1 through Table A-6.Input Setup/Hold Times Relative to ClockBasic Format:ParameterName_SIGNALwhereParameterName = T with subscript string defining the timing relationshipSIGNAL = name of Ethernet MAC signal synchronous to the clockParameterName Format:T MACxCK = Setup time before clock edgeT MACCKx = Hold time after clock edgewhere:x = {C (Control inputs)} {D (Data inputs)}Setup/Hold Time (Examples):T MACDCK_TXD /T MACCKD_TXD setup/hold times of TX data input relative to the risingedge of CLIENTEMAC#RXCLIENTCLKINwww.BDTIC.com/XILINX
