Xilinx Virtex-4 User Manual
Also see for Virtex-4 RocketIO: User guideConfiguration user guide
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Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 97UG074 (v2.2) February 22, 2010MDIO InterfaceRFigure 3-51 illustrates a third user case example that does not use the host interface, butinstead uses an external STA (MDIO master). Figure 3-51 shows this as an external deviceto the FPGA, but the EMAC’s Managements Data Input/Output (MDIO) Interface signalscan alternatively be connected directly to a STA implemented in the FPGA fabric..This functionality is obtained by asserting High TIEEMAC#CONFIGVEC[73] (MDIOenable) and pulling Low TIEEMAC#CONFIGVEC[67] (Host Interface enable) when notusing the host interface. In this case, the MDC clock must be provided through the inputport PHYEMAC#MCKIN.Accessing MDIO via the EMAC Host InterfaceThe host interface can be used to provide STA (MDIO master) functionality. The remainderof this chapter details how to access this functionality via the host interface.The MDIO interface supplies a clock to the external devices, EMAC#PHYMCLKOUTwhen the host interface is enabled. This clock is derived from the HOSTCLK signal usingthe value in the Clock Divide[5:0] configuration register. The frequency of the MDIO clockis given by the following equation:To comply with the IEEE Std 802.3-2002 specification for this interface, the frequency ofEMAC#PHYMCLKOUT should not exceed 2.5 MHz. To prevent EMAC#PHYMCLKOUTfrom being out of specification, the Clock Divide[5:0] value powers up at 000000. Whilethis value is in the register, it is impossible to enable the MDIO interface. Given this, evenif the user has enabled the host interface and the MDIO interface by tieing bothTIEEMAC#CONFIGVEC[67] and TIEEMAC#CONFIGVEC[73] High. Upon reset, theMDIO port is still disabled until a non-zero value has been written into the clock dividebits. When the host interface is disabled, the user can still access the management registersin the internal PCS/PMA layer by providing PHYEMAC#MCLKIN and tyingTIEEMAC#CONFIGVEC[73] High.Access to the MDIO interface through the management interface is shown in theFigure 3-52 timing diagram.Figure 3-51: User Case 3: External MDIO Access to the PCS/PMA SublayerAddress Filter RegistersMDIO Interface(STA MDIO Master)Configuration RegistersPCS/PMASublayer(MMDMDIO Slave)EMAC#EMAC#PHYMCLKOUTPHYEMAC#MCLKINPHYEMAC#MDINEMAC#PHYMDOUTEMAC#PHYMDTRINCExternal STA(MDIO Master)HostInterfaceIBUFIPADIOOI IOTIOPADIOBUFMDCMDIOMDIOArbitrationUG074_3_76_112705f MDCf HOSTCLK1 Clock Divide[5:0]+( ) 2×----------------------------------------------------------------------=www.BDTIC.com/XILINX |
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