Xilinx Virtex-4 User Manual
Also see for Virtex-4 RocketIO: User guideConfiguration user guide
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28 www.xilinx.com Embedded Tri-Mode Ethernet MAC User GuideUG074 (v2.2) February 22, 2010Chapter 2: Ethernet MAC Architecture RTie-Off PinsConfiguration VectorsThis section describes the 80 tie-off pins (TIEEMAC#CONFIGVEC[79:0]) used to configurethe Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC. The values of these tie-off pins areloaded into the Ethernet MAC at power-up or when the Ethernet MAC is reset.When TIEEMAC#CONFIGVEC[67] is High, the host interface is selected. Tie-off pins pre-configure the internal control registers of the Ethernet MAC. The host interface is then usedto dynamically change the register contents or to read the registers. When the hostinterface is not selected, the tie-off pins directly control the behavior of the Ethernet MAC.However, dynamically changing the register contents using the tie-off pins is notrecommended.The configuration vectors are divided into three sections: physical interface configurationvectors (Table 2-9), mode configuration vectors (Table 2-10), and MAC configurationvectors (Table 2-11). The MAC and physical interface configuration vectors can beconfigured through the host interface and are intended to be used dynamically to changeregister contents or read status registers. The mode configuration vectors preconfigure theinternal control registers (16-bit, PCS/PMA, Host, SGMII, RGMII, and MDIO interfaces)but are not dynamically reconfigurable.Table 2-9: Physical Interface Configuration PinsSignal Direction DescriptionTIEEMAC#CONFIGVEC[79] Input Reserved, set to 1.TIEEMAC#CONFIGVEC[78:74] — Only used in SGMII or 1000BASE-X modes. When MDIO and host are omitted fromthe Ethernet MAC, this alternative can be used.TIEEMAC#CONFIGVEC[78] Input PHY_RESET: Asserting this pin resets the PCS/PMA module.TIEEMAC#CONFIGVEC[77] Input PHY_INIT_AN_ENABLE: Asserting this pin enables auto-negotiation of the PCS/PMA module.TIEEMAC#CONFIGVEC[76] InputPHY_ISOLATE: Asserting this pin causes the PCS/PMAsublayer logic to behave as if it is electrically isolated from theattached Ethernet MAC, as defined in IEEE Std 802.3, Clause22.2.4.1.6. Therefore, frames transmitted by the Ethernet MACare not forwarded through the PCS/PMA. Frames received bythe PCS/PMA are not relayed to the Ethernet MAC.TIEEMAC#CONFIGVEC[75] InputPHY_POWERDOWN: Asserting this pin causes the MGT to beplaced in a Low power state. A reset must be applied to clear theLow power state.TIEEMAC#CONFIGVEC[74] Input PHY_LOOPBACK_MSB: Asserting this pin sets serial loopbackin the MGT.www.BDTIC.com/XILINX |
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