170 www.xilinx.com Embedded Tri-Mode Ethernet MAC User GuideUG074 (v2.2) February 22, 2010Appendix A: Ethernet MAC Timing Model RClock to Output DelaysBasic Format:ParameterName_SIGNALwhereParameterName = T with subscript string defining the timing relationshipSIGNAL = name of Ethernet MAC signal synchronous to the clockParameterName Format:T MACCKo = Delay time from clock edge to outputOutput Delay Time (Examples):T MACCKO_VALID rising edge of CLIENTEMAC#RXCLIENTCLKIN to RX data validsignalsT MACCKO_RXD rising edge of CLIENTEMAC#RXCLIENTCLKIN to RX data signalsCore LatencyThe latency values given in the following subsections can vary by three clock ticks in eitherdirection, due to the crossing of clock domains within the core. All clock cycles refer tocycles of the appropriate (TX or RX) client interface clock.Transmit Path LatencyThe transmit path latency is measured by counting the number of clock cycles between adata byte being placed on the client interface and its appearance at the PHY interface of theEthernet MAC. For RGMII/GMII/MII at all speeds, the latency is 13 clock cycles. SGMIIhas a latency of 13 clock cycles for 1 Gb/s and 11 clock cycles for 10/100 Mb/s.1000BASE-X has a latency of 14 clock cycles.Receive Path LatencyThe receive path latency is measured as the number of clock cycles between a byte beingdriven onto the PHY receive interface of the EMAC and its appearance at the client. ForGMII/MII, the latency is 17 clock cycles at all speeds. RGMII has a latency of 20 clockcycles. SGMII has a latency of 20 clock cycles for 1 Gb/s and 15 clock cycles for10/100 Mb/s. 1000BASE-X has a latency of 22 clock cycles.www.BDTIC.com/XILINX
