Xilinx Virtex-4 User Manual
Also see for Virtex-4 RocketIO: User guideConfiguration user guide
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Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 161UG074 (v2.2) February 22, 2010Interfacing to an FPGA Fabric-Based Statistics BlockR// Write the PHY address and PHY register to be accessed to the// dataRegLSW registermtdcr(0x0 + 13, 0x00000020);// Write the decode address for MDIO address output to the cntlReg// registermtdcr(0x0 + 14, 0x87B4);// Poll the RDYstatus registerwhile ( !(mfdcr(0x0 + 15) & 0x00000400) );Interfacing to an FPGA Fabric-Based Statistics BlockWhen the Ethernet MAC Is Implemented with the Host BusWhen the Ethernet MAC is used with the host bus, interfacing to a fabric-based statisticsblock is straight forward. Statistics information is passed from the Ethernet MAC via thestatistics vectors EMAC#CLIENTTXSTATS and EMAC#CLIENTRXSTATS. The statisticsvalues can then be read via a host interface, shared between the statistics counters and theEthernet MAC block.To share the host bus without contention, statistics counters need to use a different addressspace than the Ethernet MAC configuration registers. Conflicts with MDIO register accessare avoided by only accessing statistics counters when the signal HOSTMIIMSEL is atlogic 0. Implementation of the addressing scheme shown in Table 6-1 ensures that the hostbus can be shared without contention. This scheme provides space to address 512 statisticscounters per Ethernet MAC, using addresses 0x000 to 0x1FF.Figure 6-1 shows how to integrate the Ethernet MAC with the LogiCORE EthernetStatistics block, where the Ethernet statistics counters are accessed via the host bus. TheLogiCORE Ethernet Statistics block is used with the addressing scheme shown inTable 6-1. DS323, LogiCORE Ethernet Statistics Data Sheet, provides a a full description ofthe Ethernet Statistics LogiCORE block. Figure 6-1 illustrates how to connect EthernetStatistics blocks to both Ethernet MACs within the Ethernet MAC block. If statistics arerequired for only one Ethernet MAC, then the multiplexing between the statistics cores issimply replaced with a straight-through connection.Table 6-1: Addressing SchemeTransaction Host_miim_sel Host_addr[9]Configuration 0 1MIIM Access 1 XStatistics Access 0 0www.BDTIC.com/XILINX |
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