Xilinx Virtex-4 User Manual
Also see for Virtex-4 RocketIO: User guideConfiguration user guide
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Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 153UG074 (v2.2) February 22, 2010Auto-Negotiation InterruptR• The PHY then passes the results of the auto-negotiation process with the link partnerto the Ethernet 1000BASE-X PCS/PMA or SGMII (in SGMII mode), by leveraging the1000BASE-X auto-negotiation specification shown in Figure 5-3. This transfers theresults of the Link Partner auto-negotiation across the SGMII and this is the only auto-negotiation observed by the sub-layer.The SGMII auto-negotiation function leverages the 1000BASE-X PCS/PMA auto-negotiation function with the exception of:• The duration of the Link Timer of the SGMII auto-negotiation decreases from 10 ms to1.6 ms making the entire auto-negotiation cycle faster (see “Auto-Negotiation LinkTimer,” page 153).• The information exchanged now contains speed resolution in addition to duplexmode.The results of SGMII auto-negotiation can be used as described in “1000BASE-X Auto-Negotiation Overview,” page 151.Auto-Negotiation Link TimerThe built-in auto-negotiation Link Timer has different durations for different standards.1000BASE-X StandardThe 1000BASE-X standard Link Timer is defined as having a duration somewhere between10.354 ms and 10.387 ms.SGMII StandardThe SGMII standard Link Timer is defined as having a duration of 1.606 ms to 1.638 ms.Using the Auto-Negotiation InterruptThe auto-negotiation function has an EMAC#CLIENTANINTERRUPT port. This port isdesigned to be used with common microprocessor bus architectures (for example, theCoreConnect™ bus interfacing to a MicroBlaze design or the PPC405 processorimplemented in the Virtex-4 device).The operation of this port is enabled or disabled and cleared via Register 16 (see Table 4-19,“Vendor-Specific Register: Auto-Negotiation Interrupt Control Register (Register 16)”).• When disabled, this port is permanently driven Low.• When enabled, this port is set to logic 1 following the completion of an auto-negotiation cycle. It remains high until cleared after a zero is written to bit 16.1(Interrupt Status bit) of Register 16.www.BDTIC.com/XILINX |
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