Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 107UG074 (v2.2) February 22, 2010Gigabit Media Independent Interface (GMII) SignalsRGMII Clock Management1 Gb/s GMII OnlyFigure 4-7 shows GMII clock management when using one Ethernet MAC. The GTX_CLKhas a frequency of 125 MHz. GTX_CLK must be provided to the Ethernet MAC. This is ahigh quality 125 MHz clock that satisfies the IEEE Std 802.3-2002 requirements.The EMAC#CLIENTTXGMIIMIICLKOUT output port drives all of the transmit logicthrough a BUFG. The output of the BUFG connects to:• GMII_TXD registers in the FPGA fabric• Input port CLIENTEMAC#TXGMIIMIICLKIN• CLIENTEMAC#TXCLIENTCLKIN• TX client logicPHYEMAC#MIITXCLK must be tied to ground. The GMII_RX_CLK_# is generated fromthe PHY and is connected to PHYEMAC#RXCLK through a DCM and a BUFG. TheCLIENTEMAC#DCMLOCKED port must be tied High. The DCM is used to shift thereceived GMII clock with respect to the data, in order to sample a 2 ns setup, 0 ns holdwindow at the device pads. Phase shifting is applied to the DCM to fine tune the setup andiFigure 4-7: 1 Gb/s GMII Clock ManagementEMAC#CLIENTTXGMIIMIICLKOUTCLIENTEMAC#TXGMIIMIICLKINPHYEMAC#GTXCLKCLIENTEMAC#TXCLIENTCLKINEMAC#CLIENTTXCLIENTCLKOUTCLIENTEMAC#RXCLIENTCLKINEMAC#CLIENTRXCLIENTCLKOUTCLIENTEMAC#DCMLOCKEDPHYEMAC#RXCLKEMAC#PHYTXD[0]PHYEMAC#RXD[0]PHYEMAC#MIITXCLKEMAC#GTX_CLKTX CLIENTLOGICRX CLIENTLOGICBUFGOBUFGMII_TXD_#[0]QDGNDNCNCUG074_3_53_031009OBUFODDRGMII_TX_CLK_#D1D201GMII_RXD_#[0]GMII_RX_CLK_#IBUFIBUFGBUFGQ DCLK0CLKINCLKFBDCMwww.BDTIC.com/XILINX
