74 www.xilinx.com Embedded Tri-Mode Ethernet MAC User GuideUG074 (v2.2) February 22, 2010Chapter 3: Client, Host, and MDIO Interfaces RHost Clock FrequencyThe host clock (HOSTCLK) is used to derive the MDIO clock, MDC, and is subject to thesame frequency restrictions. See the Virtex-4 FPGA Data Sheet for the HOSTCLK frequencyparameters.Configuration RegistersThe Ethernet MAC has seven configuration registers. These registers are accessed throughthe host interface and can be written to at any time. Both the receiver and transmitter logiconly respond to configuration changes during IFGs. The configurable resets are the onlyexception, because the reset is immediate.Configuration of the Ethernet MAC is performed through a register bank accessed throughthe Host interface. Any time an address shown in Table 3-7 is accessed, a 32-bit read orwrite is performed from the same configuration word, with the exception of the read-onlyEthernet MAC mode configuration register and the RGMII/SGMII configuration register.Only the speed selection is both readable and writable in the Ethernet MAC modeconfiguration register.The configuration registers and the contents of the registers are shown in Table 3-8 throughTable 3-14.Table 3-6: Management Interface Transaction TypesTransaction HOSTMIIMSEL HOSTADDR[9]Configuration/Address Filter 0 1MDIO access 1 XTable 3-7: Configuration Registers{HOSTEMAC1SEL, HOST_ADDR[9:0]} Register Description0x200 Receiver Configuration (Word 0)0x240 Receiver Configuration (Word 1)0x280 Transmitter Configuration0x2C0 Flow Control Configuration0x300 Ethernet MAC Mode Configuration0x320 RGMII/SGMII Configuration0x340 Management ConfigurationNotes:1. HOSTEMAC1SEL acts as bit 10 of HOSTADDR.www.BDTIC.com/XILINX
