Xilinx Virtex-4 User Manual
Also see for Virtex-4 RocketIO: User guideConfiguration user guide
                                                                                                                                                                                | |
Contents
| 
Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 91UG074 (v2.2) February 22, 2010Host InterfaceRThe IRENABLE register (Address Code 0x3A4) in the host interface is used to enableinterrupt bits in the IRSTATUS register. To enable an interrupt, the corresponding bit is set.When the enable bit is cleared, the interrupt status is not updated.For examples of DCR read and write accesses, see “Interfacing to the Processor DCR” inChapter 6.Address CodeThe address codes for the Ethernet MAC registers are divided into three groups as shownin Table 3-29. The unused address codes are reserved. The detailed address codes for eachregister are described in Table 3-30. The address codes for the Ethernet MAC registers andregisters in the host interface are encoded in hardware. Address codes for statistics IPregisters and Ethernet MAC Configuration registers match the 1G Ethernet MAC Host Busaddress as specified in the Xilinx® 1G Ethernet MAC core at:http://www.xilinx.com/support/documentation/ip_documentation/gig_eth_mac_ds200.pdf .Table 3-29: Address Code Groups for DCR Host Bus AccessGroup Address Code DescriptionEMAC0 0x200 – 0x39F EMAC0 registers.Host Interface 0x3A0 – 0x3FF Host interface registers.EMAC1 0x600 – 0x79F EMAC1 registers.Notes:1. Any access to the host interface registers does not generate interrupts and does not change theRDYSTATUS register bits.Table 3-30: Detailed Address Codes for DCR Host Bus AccessAddressCodes Register Names Description Ethernet MACRegister Address R/W0x0:0x1FF Reserved.EMAC0 Registers:0x200 E0_RXCONFIGW0 Receiver configuration word 0. 0x200 R/W0x240 E0_RXCONFIGW1 Receiver configuration word 1. 0x240 R/W0x280 E0_TXCONFIG Transmitter configuration. 0x280 R/W0x2C0 E0_FLOWCONTROL Flow control configuration. 0x2C0 R/W0x300 E0_EMACCONFIG Ethernet MAC configuration. 0x300 R/W0x320 E0_RGMII_SGMII RGMII/SGMII configuration. 0x320 R0x340 E0_MGMTCONFIG Management configuration. 0x340 R/W0x380 E0_UNICASTADDRW0 Unicast address [31:0]. 0x380 R/W0x384 E0_UNICASTADDRW1 0x0000, unicast address [47:32]. 0x384 R/W0x388 E0_ADDRTABLECONFIGW0 Multicast address data [31:0] 0x388 R/W0x38C E0_ADDRTABLECONFIGW10x00, RNW,00000, ADDR[1:0],Multicast address data [47:32]0x38C R/Wwww.BDTIC.com/XILINX |
This manual is suitable for:
manualsdatabase
Your AI-powered manual search engine