Xilinx Virtex-4 User Manual
Also see for Virtex-4 RocketIO: User guideConfiguration user guide
                                                                                                                                                                                | |
Contents
| 
Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 123UG074 (v2.2) February 22, 201010/100/1000 Serial Gigabit Media Independent Interface (SGMII)R10/100/1000 Serial Gigabit Media Independent Interface (SGMII)The SGMII physical interface was defined by Cisco Systems. The data signals operate at arate of 1.25 Gb/s, and the sideband clock signals operate at 625 MHz. Due to the speed ofthese signals, differential pairs are used to provide signal integrity and minimize noise.The sideband clock signals are not implemented in the Ethernet MAC. Instead, the MGT isused to transmit and receive data with clock data recovery (CDR).When using SGMII mode, the MGT must be instantiated in the design to connect with theEthernet MAC. For more information on SGMII, refer to the Serial GMII specification v1.7.This interface only supports full-duplex operation.SGMII RX Elastic BufferThe RX elastic buffer can be implemented in one of two ways:• Using the buffer present in the MGTs• Using a larger buffer that is implemented in the FPGA logicThis section describes the selection and implementation of two options in the followingsubsections:• “Using the MGT RX Elastic Buffer”• “Using the FPGA Logic Elastic Buffer”RX Elastic Buffer ImplementationsSelecting the Buffer Implementation from the GUIThe GUI for the Ethernet MAC provides two alternative options under the heading“SGMII Capabilities.” These options are:1. 10/100/1000 Mb/s (clock tolerance compliant with Ethernet specification).Default setting; provides the implementation using the RX elastic buffer in FPGAfabric. This alternative RX elastic buffer utilizes a single block RAM to create a buffertwice as large as the one present in the RocketIO™ transceivers, subsequentlyconsuming extra logic resources. However, this default mode provides reliable SGMIIoperation under all conditions.2. 10/100/1000 Mb/s (restricted tolerance for clocks) OR 100/1000 Mb/s.Uses the RX elastic buffer present in the RocketIO transceivers. This is half the size andcan potentially under- or overflow during SGMII frame reception at 10 Mb/soperation. However, there are logical implementations where this can be provenreliable; if so, it is favored because of its lower logic utilization.Option 1, the default mode, provides the implementation using the RX elastic buffer in theFPGA logic. This alternative RX elastic buffer utilizes a single block RAM to create a bufferthat is twice as large as the one present in the MGT, therefore consuming extra logicresources. However, this default mode provides reliable SGMII operation.Option 2 uses the RX elastic buffer in the MGTs. This buffer, which is half the size of thebuffer in Option 1, can potentially underflow or overflow during SGMII frame reception at10 Mb/s operation (see “The FPGA RX Elastic Buffer Requirement”). However, in logicalimplementations where this case is proven reliable, this option is preferred because of itslower logic utilization.www.BDTIC.com/XILINX |
This manual is suitable for:
manualsdatabase
Your AI-powered manual search engine