Xilinx Virtex-4 User Manual
Also see for Virtex-4 RocketIO: User guideConfiguration user guide
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Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 27UG074 (v2.2) February 22, 2010Ethernet MAC Signal DescriptionsRDCR Bus Interface SignalsTable 2-6 outlines the DCR bus interface signals.Reset and CLIENTEMAC#DCMLOCKED SignalsTable 2-7 describes the Reset signal.Table 2-8 describes the CLIENTEMAC#DCMLOCKED signal.Table 2-6: DCR Bus SignalsSignal Direction DescriptionDCREMACCLK Input Clock for the DCR interface from the PowerPC processor.DCREMACABUS[8:9] Input Two LSBs of the DCR address bus. Bits[0] through [7] are decodedin conjunction with the PowerPC block.DCREMACREAD Input DCR read request.DCREMACWRITE Input DCR write request.DCREMACDBUS[0:31] Input DCR write data bus.DCREMACENABLE(1) InputWhen using the DCR bus, this signal is connected directly to thePPC405 output port DCREMACENABLER for DCR bus access.When using the host bus interface, the signal is connected to thelogic ground.EMACDCRDBUS[0:31] Output DCR read data bus.EMACDCRACK Output DCR acknowledge.DCRHOSTDONEIR (1) Output Interrupt signal to the PowerPC processor when the EthernetMAC register access is done.Notes:1. All the DCR bus signals are internally connected to the PowerPC processor except for the DCREMACENABLE andDCRHOSTDONEIR signals.Table 2-7: Reset SignalSignal Direction DescriptionReset Input Asynchronous reset of both Ethernet MACs.Table 2-8: CLIENTEMAC#DCMLOCKED SignalSignal Direction DescriptionCLIENTEMAC#DCMLOCKED InputIf a DCM is used to derive any of the clock signals, the LOCKEDport of the DCM must be connected to theCLIENTEMAC#DCMLOCKED port. The Ethernet MAC is heldin reset until CLIENTEMAC#DCMLOCKED is asserted High.If a DCM is not used, both CLIENTEMAC#DCMLOCKED portsfrom EMAC0 and EMAC1 must be tied High.If any Ethernet MAC is not used, CLIENTEMAC#DCMLOCKEDmust be tied to High.www.BDTIC.com/XILINX |
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