Here is valid:n Rising edge: Edge 0-1n Falling edge: Edge 1-0n The input delay can be configured per channel in groups of 4.n An input delay of 0.1ms is only possible with "fast" inputs, which have a max. inputfrequency of 100kHzÄ ‘X4: Connector’ page 45. Within a group, the input delay forslow inputs is limited to 0.5ms.n Range of values: 0.1ms / 0.5ms / 3ms / 15ms12.6.4 Digital output12.6.4.1 Overviewn 12xDC 24V, 0.5An Sub module ‘DI16/DO12’nÄ Chap. 5.5 ‘Digital output’ page 12612.6.4.2 Parametrization in SPEED7 Studio12.6.4.2.1 ‘I/O addresses’Sub module Output address Access AssignmentDI16/DO12 136 BYTE Digital output Q+0.0 ... Q+0.7 (X5)137 BYTE Digital output Q+1.0 ... Q+1.3 (X5)12.6.5 Counter12.6.5.1 Overviewn 4 channelsn Sub module: ‘Counter’nÄ Chap. 5.6 ‘Counting’ page 12812.6.5.2 Parametrization in SPEED7 Studio12.6.5.2.1 ‘I/O addresses’Sub module Input address Access AssignmentCount 816 DINT Channel 0: Counter value / Frequency value820 DINT Channel 1: Counter value / Frequency value824 DINT Channel 2: Counter value / Frequency value828 DINT Channel 3: Counter value / Frequency valueInput delayVIPA System SLIO Configuration with VIPA SPEED7 StudioDeployment I/O periphery > CounterHB300 | CPU | 013-CCF0R00 | en | 19-30 279
