PulseTimeOndelayOutput 1PulseTimeOndelayOutput 2PulseTimeOndelayOutput 3Input 17Input 32Input 1Input 16IEC09000612_1_en.vsd³1³1³1³1&&&&&&ModeOutput1³1ModeOutput2³1ModeOutput3tttOffdelayttttOffdelaytOffdelaytIEC09000612 V1 ENFigure 164: Trip matrix internal logicOutput signals from TMAGGIO are typically connected to other logic blocks ordirectly to output contacts in the IED. When used for direct tripping of the circuitbreaker(s) the pulse time delay shall be set to approximately 0.150 seconds in orderto obtain satisfactory minimum duration of the trip pulse to the circuit breaker tripcoils.12.3 Configurable logic blocks12.3.1 Standard configurable logic blocks12.3.1.1 FunctionalityA number of logic blocks and timers are available for the user to adapt theconfiguration to the specific application needs.• OR function block.• INVERTER function blocks that inverts the input signal.• PULSETIMER function block can be used, for example, for pulse extensionsor limiting of operation of outputs.1MRK 502 034-UEN - Section 12Logic323Technical Manual
