Installing a memory moduleThis information provides instructions for installing a memory module.About this taskThe following notes describe the types of dual inline memory modules (DIMMs)that the server supports and other information that you must consider when youinstall DIMMs (see “System-board optional-device connectors” on page 33 for thelocation of the DIMM connectors):v Confirm that the server supports the DIMM that you are installing (seehttp://www.ibm.com/systems/info/x86servers/serverproven/compat/us/).v When you install or remove DIMMs, the server configuration informationchanges. When you restart the server, the system displays a message thatindicates that the memory configuration has changed. You can use the Setuputility to view the server configuration information, see “Using the Setup utility”on page 142 for more information.v The server supports only industry-standard double-data-rate 3 (DDR3),PC3-12800R 1600 MHz, PC3L-10600R-999 1333 MHz or PC3L-10600 1333 MHzLoad Reduced (LR), single-rank, dual-rank, or quad-rank, registered,synchronous dynamic random-access memory (SDRAM) dual inline memorymodules (DIMMs) with error correcting code (ECC).– The specifications of a DDR3 DIMM are on a label on the DIMM, in thefollowing format.gGB eRxf-PC3-wwwwwm-a-b-c-dwhere:- gGB is the total capacity of the DIMM (for example, 1GB, 2GB, or 4GB)- eR is the number of ranks1R = single-rank2R = dual-rank4R = quad-rank- xf is the device organization or bit width (for example, x4, x8, or x16)4 = x4 organization (4 DQ lines per SDRAM)8 = x8 organization16 = x16 organization- wwwww is the DIMM bandwidth, in MBps6400 = 6.40 GBps (PC3-800 SDRAMs, 8-byte primary data bus)8500 = 8.53 GBps (PC3-1066 SDRAMs, 8-byte primary data bus)10600 = 10.66 GBps (PC3-1333 SDRAMs, 8-byte primary data bus)12800 = 12.80 GBps PC3-1600 SDRAMs, 8-byte primary data bus)- m is the DIMM typeE = Unbuffered DIMM (UDIMM) with ECC (x72-bit module data bus)R = Registered DIMM (RDIMM)U = Unbuffered DIMM with no ECC (x64-bit primary data bus)- a is the CAS latency, in clocks at maximum operating frequency- b is the JEDEC SPD Revision Encoding and Additions level- c is the reference design file for the design of the DIMM- d is the revision number of the reference design of the DIMMChapter 2. Installing optional devices 43
