Enhanced Queued Analog-to-Digital Converter (EQADC)MPC5644A Microcontroller Reference Manual, Rev. 6Freescale Semiconductor 100325.2.2 Block diagramFigure 25-1 is the block diagram for the EQADC.Figure 25-1. EQADC Block DiagramFigure 25-1 shows the primary components inside the EQADC. The EQADC consists of the FIFO ControlUnit which controls the CFIFOs and the RFIFOs, the ADC Control Logic which controls the two on-chipADCs, the EQADC Synchronous Serial Interface (EQADC SSI) which allows communication with anexternal device, and the EQADC Parallel Side Interface (EQADC PSI) which allows communication withon-chip eQADC companion modules1. There are 6 CFIFOs and 6 RFIFOs, each with 4 entries, exceptCFIFO0 that can have 8 entries.1.Decimation filters A and B and Reaction moduleAN8/ANWAN9/ANX/TBIASAN10/ANYAN11/ANZAN0/DAN0+AN1/DAN0-AN2/DAN1+AN3/DAN1-AN4/DAN2+AN5/DAN2-AN6/DAN3+AN7/DAN3-PriorityDecoderExternal DeviceSDSFCKSDOSDIADC0ADC1BIASGENREFBYPCCFIFOxNOTE: x=0, 1, 2, 3, 4, 532 bitsCQueue yRQueue ySystemRFIFOx16 bitsCBuffer0CBuffer1EQADCFIFO ControlMUXControlLogicSynchronous SerialChannelVDDAVSSAVRHVRLMA0MA1MA2y=0, 1, 2, 3, ...DMA andRequestsNumberADC ControlInterface (EQADC SSI)EQADCInterruptDMA TransactionDone SignalsEQADC SSITransmit BufferUnitLogicAN12/T50PVREFAN13/T25PVREFAN15AN14/T75PVREFPre-ChargeREFGENParallel Side Interface(EQADC PSI)EQADCOn-ChipDigital Signal ProcessorAbortContAbortContMemoryResultFormatandCalibra-tionETRIGx, ATRIGFIL BYPASSxAN16/AN17AN19AN18AN20-39MUX MUX
