Deserial Serial Peripheral Interface (DSPI)MPC5644A Microcontroller Reference Manual, Rev. 6Freescale Semiconductor 131530.9.8 Timed serial bus (TSB)The DSPI can be programmed in Timed Serial Bus configuration by setting the TSBC bit in theDSPI_DSICR. See Section 30.8.2.11, DSPI DSI Configuration Register (DSPI_DSICR)” for details.TSB configuration provides the Micro Second Channel (MSC) downstream channel support.The MSC upstream channel is not supported by the DSPI, but can be supported by any available SerialCommunication Controller (SCI or UART) in the device.To work in TSB mode the DSPI must be in master mode and in DSI (DCONF = 0b01) or CSI(DCONF = 0b10) configuration. Both Continuous and Non Continuous Serial Communication Clock(controlled by bit DSPI_MCR[CONT_SCKE]) are supported in the TSB mode.Figure 30-50 shows the signals used in the TSB interface.In the TSB configuration the DSPI is able to send from 4 to 34 bits MSC data frames (4 to 32 serializeddata bits and up to 2 Data Selection zero bits). The serialized data bits source can be either:• the DSPI DSI Alternate Serialization Data Register (DSPI_ASDR), written by the host software,• Parallel Input pin states latched into the DSPI DSI Serialization Data Register (DSPI_SDR).DSPI_DSICR TXSS bit or DSPI_SSR bits define the source of the data.The Least Significant Bits of the DSPI_ASDR or DSPI_SDR registers are selected to be serialized if thedata frame is set to less than 32 bits.Figure 30-50. DSPI usage in the TSB configurationThe PCS signals are driven together with SOUT. The tCSC and t ASC delays are not available. Delay afterTransfer (DT) is set in SCK clock periods as a binary number formed by concatenation of theDSPI_CTARn PDT and DT fields plus one, allowing to set DT from 1 to 64 serial clock periods. DT fieldprovides least significant bits and PDT field provides most significant bits of the Delay after Transfer.SCKSOUTPCS1PCS2Slave1Slave2DINCLKCSCLKDINCSDSPI downstream channel
