IntroductionMPC5644A Microcontroller Reference Manual, Rev. 638 Freescale Semiconductor— Pad configuration control for virtual I/O via DSPI serialization• System reset monitoring and generation— Power-on reset support— Reset status register provides last reset source to software— Glitch detection on reset input— Software controlled reset assertion• External interrupt— Rising or falling edge event detection— Programmable digital filter for glitch rejection— Critical Interrupt request— Non-Maskable Interrupt request• GPIO— Centralized control of I/O and bus pins— Virtual GPIO via DSPI serialization (requires external deserialization device)— Dedicated input and output registers for setting each GPIO and Virtual GPIO pin• Internal multiplexing— Allows serial and parallel chaining of DSPIs— Allows flexible selection of eQADC trigger inputs— Allows selection of interrupt requests between external pins and DSPI1.4.9 Flash memoryThe MPC5644A provides up to 4 MB of programmable, non-volatile, flash memory. The non-volatilememory (NVM) can be used to store instructions or data, or both. The flash module includes a FetchAccelerator that optimizes the performance of the flash array to match the CPU architecture. The flashmodule interfaces the system bus to a dedicated flash memory array controller. For CPU ‘loads’, DMAtransfers and CPU instruction fetch, it supports a 64-bit data bus width at the system bus port, and 128-and 256-bit read data interfaces to flash memory. The module contains a prefetch controller whichprefetches sequential lines of data from the flash array into the buffers. Prefetch buffer hits allow no-waitresponses.The flash memory provides the following features:• Supports a 64-bit data bus for instruction fetch, CPU loads and DMA access. Byte, halfword, wordand doubleword reads are supported. Only aligned word and doubleword writes are supported.• Fetch Accelerator— Architected to optimize the performance of the flash— Configurable read buffering and line prefetch support— Four-entry 256-bit wide line read buffer— Prefetch controller• Hardware and software configurable read and write access protections on a per-master basis
