Device Performance OptimizationMPC5644A Microcontroller Reference Manual, Rev. 6118 Freescale Semiconductor• Use of DMA rather than CPU to transfer data efficiently• Use of DMA service requests rather than CPU interrupts to avoid software polling• Off-loading tasks from the CPU to the eTPU2 or eDMA• Careful allocation of cache usage for code and data ranges, particularly when using with externalmemories.Different items in this list will have different performance impacts in a real system. Features like thesystem cache, the FMPLL and the flash access times tend to provide the most significant performanceimpacts in terms of hardware settings.The subsequent sections in this chapter describe how to configure and use these features.6.3 Configuring hardware features6.3.1 Branch target buffer (BTB)6.3.1.1 DescriptionTo resolve branch instructions and improve the accuracy of branch predictions the e200z4 core implementsa dynamic branch prediction mechanism using a branch target buffer (BTB), a fully associative addresscache of branch target addresses. Its purpose is to accelerate the execution of software loops with somepotential change of flow within the loop body. In addition, the BTB on the e200z4 has a subroutine callstack that speeds up indirect branches.6.3.1.2 Recommended configurationBy default, this BTB is disabled following negation of reset. It is controlled by the Branch Unit Controland Status Register (BUCSR). The BTB’s contents should be flushed and invalidated by writingBUCSR[BBFI] = 1, and it may be enabled by subsequently writing BUCSR[BPEN] = 1.Additional control is available in BUCSR[BPRED] and BUCSR[BALLOC] to control whether forward orbackward branches (or both) are candidates for entry into the BTB, and thus for branch prediction. Bydefault the BUCSR[BPRED] and BUCSR[BALLOC] fields are set to 0b00, which enables forward andbackward branch prediction. It is recommended to not disable branch prediction although for extremelyfine tuning of a given application the optimum setting of BUCSR[BPRED] and BUCSR[BALLOC]should be assessed..0BBFI0BALLOC0BPREDBPEN0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31SPR - 1013; Read/Write; Reset - 0x0Figure 6-1. Branch Unit Control and Status Register (BUCSR)
