Memory Protection Unit (MPU)MPC5644A Microcontroller Reference Manual, Rev. 6272 Freescale Semiconductorassignments. For an example of the use of overlapping region descriptors, see Section 13.7, ApplicationInformation.When the MPU causes a termination error to occur, the effect on the system depends on the bus masterrequesting the access. If the error was caused by a core access, a machine check is taken. If the error wascaused by an eDMA access, an eDMA source or destination error occurs in the eDMA controller, whichcan be enabled to provide an interrupt request through the INTC. If the error was caused by a FlexRayaccess, a controller host interface (CHI) illegal system memory access error occurs in the FlexRaycontroller, which can be enabled to provide an interrupt request to the INTC.13.6 Initialization InformationThe reset state of MPU_CESR[VLD] disables the entire module. While the MPU is disabled, all accessesfrom all bus masters are allowed. This state also minimizes the power dissipation of the MPU. The powerdissipation of each access evaluation macro is minimized when the associated region descriptor is markedas invalid or when MPU_CESR[VLD] = 0.Typically the appropriate number of region descriptors (MPU_RGDn) are loaded at system startup,including the setting of the MPU_RGDn.Word3[VLD] bits, before MPU_CESR[VLD] is set, enabling themodule. This approach allows all the loaded region descriptors to be enabled simultaneously. Once theMPU is enabled, if a memory reference does not hit in any region descriptor, the attempted access isterminated with an error.13.7 Application InformationIn an application’s system, interfacing with the MPU can generally be classified into the followingactivities:1. Creation of a new memory region requires loading the appropriate region descriptor into anavailable register location. When a new descriptor is loaded into a RGDn, it would typically beperformed using four 32-bit word writes. As discussed in Section 13.4.2.4.4, MPU RegionDescriptor n, Word 3 (MPU_RGDn.Word3), the hardware assists in the maintenance of the validbit, so if this approach is followed, there are no coherency issues associated with the multi-cycledescriptor writes. Deletion/removal of an existing memory region is performed by clearingMPU_RGDn.Word3[VLD].2. If only the access rights for an existing region descriptor need to change, a 32-bit write to thealternate version of the access control word (MPU_RGDAACn) would typically be performed.Writes to the region descriptor using this alternate access control location do not affect the validbit, so there are, by definition, no coherency issues involved with the update. The access rightsassociated with the memory region switch instantaneously to the new value as the IPS writecompletes.3. If the region’s start and end addresses are to be changed, this would typically be performed bywriting a minimum of three words of the region descriptor: MPU_RGDn.Word{0,1,3}, where thewrites to Word0 and Word1 redefine the start and end addresses respectively and the write toWord3 re-enables the region descriptor valid bit. In many situations, all four words of the regiondescriptor would be rewritten.
