Decimation FilterMPC5644A Microcontroller Reference Manual, Rev. 6Freescale Semiconductor 117526.2.3.3 PSI Input Mixed modeIn this mode the input is selected from the PSI slave-bus interface, but the output is directed to the deviceslave-bus interface, where it can be read by the CPU or DMA.26.2.3.4 PSI Output Mixed modeThis mode works inverted from the PSI Input Mixed Mode: the input is selected from the device slave-businterface, fed either by the CPU or DMA, and the output is directed to the PSI slave-bus interface. If aneQADC is connected to the PSI interface, the output is directed to an RFIFO selected by the tag field inthe DECFILTER_IB register (see Section 26.4.2.5, Decimation Filter Interface Input Buffer Register(DECFILTER_IB)”).26.2.3.5 Cascade modeCascade mode is a filter structure mode with two or more individual filter blocks connected in a chain toform a more complex filter function. The output result of the first block (head block) is connected to theinput of the next block (middle or tail block) to be filtered again. More details in Section 26.5.16, Cascademode description”.26.2.3.6 Low Power modeLow power mode corresponds to the module disable mode or stop mode. In the module disable mode thePSI slave-bus line is disabled and it is not possible to enter Freeze mode. The system clock is stopped. Andin stop mode, the system clock is also stopped.26.2.3.7 Freeze modeThis mode is also known as debug mode. All filter action is frozen, either through software or by thehardware SoC debug request signal. If a freeze request comes when the filter is processing an input, itenters freeze mode only after the processing finishes.26.3 External signal descriptionNOTEThe Decimation Filter does not provide metastability protection norfiltering for these signals.26.3.1 Decimation trigger signalThis signal is used to control the output of the decimation filter, allowing decimation to be drivenexternally. For more details, see Section 26.5.4.2, Triggered output result description”.26.3.2 Integrator enable signalThis signal is used to enable the hardware integrator. For more details, see Section 26.5.15.4, Integratorenabling and halting”.
