Interrupt Controller (INTC)MPC5644A Microcontroller Reference Manual, Rev. 6348 Freescale Semiconductor15.4.1 Register descriptionsExcept INTC_SSCIn and INTC_PSRn registers, all registers are 32-bits wide. Any combination ofaccessing the 4 bytes of a register with a single access is supported, provided that the access does not crossthe register boundary. These supported accesses include types and sizes of 8 bits, aligned 16 bits, andaligned 32 bits.Although INTC_SSCIn and INTC_PSRn are 8-bits wide, they can be accessed with a single 16-bit or32-bit access, provided that the access does not cross a 32-bit boundary.In the software vector mode, the side effects of a read of the INTC interrupt acknowledge register(INTC_IACKR) are the same regardless of the size of the read. In either software or hardware vectormode, the size of a write to the INTC end-of-interrupt register (INTC_EOIR) does not affect the operationof the write.Table 15-2. INTC Memory MapAddress Register Name Register Description BitsBase (0xFFF4_8000) INTC_MCR INTC module configuration register 32Base + 0x0004 — Reserved —Base + 0x0008 INTC_CPR INTC current priority register 32Base + 0x000C — Reserved —Base + 0x0010 INTC_IACKR INTC interrupt acknowledge register 11 When the HVEN bit in the INTC_MCR is asserted, a read of the INTC_IACKR has no side effects.32Base + 0x0014 — Reserved —Base + 0x0018 INTC_EOIR INTC end-of-interrupt register 32Base + 0x001C — Reserved —Base + 0x0020 INTC_SSCIR0 INTC software set/clear interrupt register 0 8Base + 0x0021 INTC_SSCIR1 INTC software set/clear interrupt register 1 8Base + 0x0022 INTC_SSCIR2 INTC software set/clear interrupt register 2 8Base + 0x0023 INTC_SSCIR3 INTC software set/clear interrupt register 3 8Base + 0x0024 INTC_SSCIR4 INTC software set/clear interrupt register 4 8Base + 0x0025 INTC_SSCIR5 INTC software set/clear interrupt register 5 8Base + 0x0026 INTC_SSCIR6 INTC software set/clear interrupt register 6 8Base + 0x0027 INTC_SSCIR7 INTC software set/clear interrupt register 7 8Base + (0x0028–0x003F) — Reserved —Base + (0x0040–0x01A7) INTC_PSRn INTC priority select registers 2 0–4852 The PRI fields are “Reserved” for peripheral interrupt requests whose vectors are labeled as Reserved in Table 15-7.8
