FlexCAN ModuleMPC5644A Microcontroller Reference Manual, Rev. 61436 Freescale SemiconductorThe sensitivity to CAN bus activity can be modified by applying a low-pass filter function to the Rx CANinput line while in Stop Mode. See the WAK_SRC bit in Section 32.4.5.1, Module Configuration Register(MCR). This feature can be used to protect FlexCAN from waking up due to short glitches on the CANbus lines. Such glitches can result from electromagnetic interference within noisy environments.32.5.10 InterruptsThe module can generate up to 70 interrupt sources (64 interrupts due to message buffers and 6 interruptsdue to Ored interrupts from message buffers, Bus Off, Error, Tx Warning, Rx Warning and Wake Up). Thenumber of actual sources depends on the configured number of Message Buffers.Each one of the message buffers can be an interrupt source, if its corresponding bit in the IMRL or IMRHregister is set. There is no distinction between Tx and Rx interrupts for a particular buffer, under theassumption that the buffer is initialized for either transmission or reception. Each of the buffers hasassigned a flag bit in the IFRL or IFRH register. The bit is set when the corresponding buffer completes asuccessful transmission/reception and is cleared when the CPU writes it to ‘1’ (unless another interrupt isgenerated at the same time).NOTEIt must be guaranteed that the CPU only clears the bit causing the currentinterrupt. For this reason, bit manipulation instructions (BSET) must not beused to clear interrupt flags. These instructions may cause accidentalclearing of interrupt flags which are set after entering the current interruptservice routine.If the Rx FIFO is enabled (MCR[FEN] set), the interrupts corresponding to MBs 0 to 7 have a differentbehavior. Bit 7 of the IFRL becomes the “FIFO Overflow” flag; bit 6 becomes the FIFO Warning flag, bit5 becomes the “Frames Available in FIFO flag” and bits 4–0 are unused. See Section 32.4.5.12, InterruptFlags 1 Register (IFRL) for more information.A combined interrupt for all message buffers is also generated by an Or of all the interrupt sources frommessage buffers. This interrupt gets generated when any of the message buffers generates an interrupt. Inthis case the CPU must read the IFRL or IFRH register to determine which message buffer caused theinterrupt.The other five interrupt sources (Bus Off, Error, Tx Warning, Rx Warning and Wake Up) generateinterrupts like the message buffer ones, and can be read from the Error and Status Register. The Bus Off,Table 32-22. Wake-up from Stop ModeSLF_WAK WAK_MSK MCU clocks enabled Wake-up interruptgenerated0 0 No No0 1 No No1 0 No No1 1 Yes Yes
