Enhanced Direct Memory Access Controller (eDMA)MPC5644A Microcontroller Reference Manual, Rev. 6138 Freescale Semiconductor• All data movement via dual-address transfers: read from source, write to destination— Programmable source, destination addresses, transfer size, and support for enhancedaddressing modes• Both 32- and 64-channel implementation performs complex data transfers with minimalintervention from a host processor— 32 bytes of data registers, used as temporary storage to support burst transfers(refer to SSIZE bit)— Connections to the crossbar switch for bus mastering the data movement• Transfer control descriptor organized to support two-deep, nested transfer operations— An inner data transfer loop defined by a minor byte transfer count— An outer data transfer loop defined by a major iteration count• Channel activation via 1 of 3 methods:— Explicit software initiation— Initiation via a channel-to-channel linking mechanism for continuous transfers— Peripheral-paced hardware requests (one per channel)All three methods require one activation per execution of the minor loop• Support for fixed-priority and round-robin channel arbitration• Support for complex data structures• Support to cancel transfers via software• Channel completion reported via optional interrupt requests— 1 interrupt per channel, optionally asserted at completion of major iteration count— Error terminations are optionally enabled per channel and logically summed together to forma single error interrupt (32-channel eDMA) or two error interrupts (64-channel eDMA).• Support for scatter-gather DMA processing• Support for complex data structures• Any channel can be programmed to be suspended by a higher priority channel’s activation, beforecompletion of a minor loop.8.1.3 Modes of operationThere are two main operating modes of eDMA: normal mode and debug mode. These modes are brieflydescribed in this section.8.1.3.1 Normal modeIn normal mode, the eDMA is used to transfer data between a source and a destination. The source anddestination can be a memory block or an I/O block capable of operation with the eDMA.
