IntroductionMPC5644A Microcontroller Reference Manual, Rev. 6Freescale Semiconductor 33— 688 ns minimum conversion time• On-chip CAN/SCI/FlexRay Bootstrap loader with Boot Assist Module (BAM)• Nexus— Class 3+ for the e200z4 core— Class 1 for the eTPU• JTAG (5-pin)• Development Trigger Semaphore (DTS)— Register of semaphores (32-bits) and an identification register— Used as part of a triggered data acquisition protocol— EVTO pin is used to communicate to the external tool• Clock generation— On-chip 4–40 MHz main oscillator— On-chip FMPLL (frequency-modulated phase-locked loop)• Up to 120 general purpose I/O lines— Individually programmable as input, output or special function— Programmable threshold (hysteresis)• Power reduction mode: slow, stop and stand-by modes• Flexible supply scheme— 5 V single supply with external ballast— Multiple external supply: 5 V, 3.3 V and 1.2 V• Packages— 176 LQFP— 208 MAPBGA— 324 TEPBGA— 496-pin CSP (calibration tool only)1.4.1 Feature details1.4.2 e200z4 coreMPC5644A devices have a high performance e200z448n3 core processor:• Dual issue, 32-bit Power Architecture embedded category CPU• Variable Length Encoding Enhancements• 8 KB instruction cache: 2- or 4- way set associative instruction cache• Thirty-two 64-bit general purpose registers (GPRs)• Memory management unit (MMU) with 24-entry fully-associative translation look-aside buffer(TLB)• Harvard Architecture: Separate instruction bus and load/store bus
