Interrupt Controller (INTC)MPC5644A Microcontroller Reference Manual, Rev. 6368 Freescale Semiconductor15.5.1.1 Peripheral interrupt requestsAn interrupt event in a peripheral’s hardware sets a flag bit, which resides in that peripheral. The interruptrequest from the peripheral is driven by that flag bit.The time from when the peripheral starts to drive its peripheral interrupt request to the INTC to the timethat the INTC starts to drive the interrupt request to the processor is three clocks.15.5.1.2 Software configurable interrupt requestsThe software set/clear interrupt registers (INTC_SSCIRx_x) support the setting or clearing ofsoftware-configurable interrupt requests. These registers contain eight independent sets of bits to set andclear a corresponding flag bit by software. With the exception of being set by software, this flag bit behavesthe same as a flag bit set within a peripheral. This flag bit generates an interrupt request within the INTCjust like a peripheral interrupt request.An interrupt request is triggered by software writing a 1 to the SETn bit in INTC software set/clearinterrupt registers (INTC_SSCIR0–INTC_SSCIR7). This write sets a CLRn flag bit that generates aninterrupt request. The interrupt request is cleared by writing a 1 to the CLRn bit. Specific behavior includesthe following:• Writing a 1 to SETn leaves SETn unchanged at 0 but sets the flag bit (CLRn bit).• Writing a 0 to SETn has no effect.• Writing a 1 to CLRn clears the flag (CLRn) bit.• Writing a 0 to CLRn has no effect.• If a 1 is written to a pair of SETn and CLRn bits at the same time, the flag (CLRn) is set, regardlessof whether CLRn was asserted before the write.The time from the write to the SETn bit to the time that the INTC starts to drive the interrupt request to theprocessor is four clocks.15.5.1.3 Unique vector for each interrupt request sourceEach peripheral and software configurable interrupt request is assigned a hardwired unique 9-bit vector.Software configurable interrupts 0–7 are assigned vectors 0–7, respectively. The peripheral interruptrequests are assigned vectors 8 to as high as needed to cover all of the peripheral interrupt requests.15.5.2 Priority managementThe asserted interrupt requests are compared to each other based on their PRIn values in INTC priorityselect registers (INTC_PSR0–INTC_PSR485). The result of the comparison also is compared to PRI inINTC current priority register (INTC_CPR). The results of those comparisons are used to manage thepriority of the ISR being executed by the processor. The LIFO also assists in managing the priority.15.5.2.1 Current priority and preemptionThe priority arbitrator, selector, encoder, and comparator submodules shown in Figure 15-1 are used tocompare the priority of the asserted interrupt requests to the current priority. If the priority of any asserted
