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NXP Semiconductors MPC5644A Reference Manual

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. Table Of Contents
  17. Table Of Contents
  18. Table Of Contents
  19. Table Of Contents
  20. Table Of Contents
  21. Table Of Contents
  22. The MPC5644A Microcontroller Family
  23. MPC5644A and MPC5642A Device Comparison
  24. Device block diagram
  25. Feature summary
  26. Feature details
  27. Crossbar Switch (XBAR)
  28. Interrupt controller
  29. Memory protection unit (MPU)
  30. FMPLL
  31. Flash memory
  32. eMIOS
  33. Reaction module
  34. DSPI
  35. eSCI
  36. FlexCAN
  37. FlexRay
  38. Software watchdog timer (SWT)
  39. Error correction status module (ECSM)
  40. Power management controller (PMC)
  41. Development Trigger Semaphore (DTS)
  42. Introduction
  43. Chapter 3
  44. Signal Properties
  45. Signal Details
  46. Reset sources
  47. Reset vector
  48. FMPLL lock gating signal
  49. Power-on reset (POR)
  50. Loss of clock
  51. JTAG reset
  52. Reset configuration
  53. Reset configuration timing
  54. Reset weak pull up/down configuration
  55. Overview
  56. Clock architecture
  57. Block diagram
  58. FMPLL modes of operation
  59. Configuring hardware features
  60. Frequency-modulated PLL
  61. Flash bus interface unit
  62. Cache
  63. Memory management unit (MMU)
  64. Application software
  65. Signal processing extension
  66. Hardware single precision floating point
  67. Peripherals and general application guidelines
  68. Performance optimization checklist
  69. Microarchitecture summary
  70. Instruction unit features
  71. Integer unit features
  72. e200z4 system bus features
  73. Modes of operation
  74. External signal description
  75. Register descriptions
  76. Functional description
  77. eDMA basic data flow
  78. Initialization / Application information
  79. DMA programming errors
  80. DMA request assignments
  81. DMA arbitration mode considerations
  82. DMA transfer
  83. TCD status
  84. Channel linking
  85. Dynamic programming
  86. Features
  87. XBAR registers
  88. XBAR register descriptions
  89. Coherency
  90. Function
  91. Priority assignment
  92. PBRIDGE features
  93. PBRIDGE signal description
  94. Access timing
  95. Initialization and application information
  96. Module memory map
  97. UTest Mode
  98. Flash Programming
  99. Flash Erase
  100. Flash shadow block
  101. Flash reset
  102. Initialization Information
  103. Information Specific to This Device
  104. Detailed signal descriptions
  105. Signal output buffer enable logic by mode
  106. External bus operations
  107. Initialization/Application information
  108. Running with asynchronous memories
  109. Connecting an mcu to multiple memories
  110. EBI operation with reduced Pinout MCUs
  111. Summary of Differences from MPC5xx
  112. Priority management
  113. Details on handshaking with processor
  114. ISR, RTOS, and task hierarchy
  115. Order of execution
  116. Priority ceiling protocol
  117. deadlines
  118. Lowering priority within an ISR
  119. Examining LIFO contents
  120. Signal description
  121. Memory map and register descriptions
  122. MCU ID Register 2 (SIU_MIDR2)
  123. MCU ID Register (SIU_MIDR)
  124. Reset Status Register (SIU_RSR)
  125. System Reset Control Register (SIU_SRCR)
  126. External Interrupt Status Register (SIU_EISR)
  127. DMA/Interrupt Request Enable Register (SIU_DIRER)
  128. DMA/Interrupt Request Select Register (SIU_DIRSR)
  129. Overrun Status Register (SIU_OSR)
  130. IRQ Rising-Edge Event Enable Register (SIU_IREER)
  131. External IRQ Falling-Edge Event Enable Register (SIU_IFEER)
  132. IRQ Filtered Input Register (SIU_IFIR)
  133. Pad Configuration Registers (SIU_PCR)
  134. GPIO Pin Data Output Registers (SIU_GPDO0_3 – SIU_GPDO412_413)
  135. GPIO Pin Data Input Registers (SIU_GPDI0_3 – SIU_GPDI_232)
  136. eQADC Trigger Input Select Register (SIU_ETISR)
  137. External IRQ Input Select Register (SIU_EIISR)
  138. DSPI Input Select Register (SIU_DISR)
  139. IMUX Select Register 3 (SIU_ISEL3)
  140. IMUX Select Register 8 (SIU_ISEL8)
  141. IMUX Select Register 9 (SIU_ISEL9)
  142. IMUX Select Register 10 (SIU_ISEL10)
  143. Chip Configuration Register (SIU_CCR)
  144. External Clock Control Register (SIU_ECCR)
  145. Compare A High Register (SIU_CARH)
  146. Compare B High Register (SIU_CBRH)
  147. System Clock Register (SIU_SYSDIV)
  148. Halt Register (SIU_HLT)
  149. Halt Acknowledge Register (SIU_HLTACK)
  150. Core MMU PID Control Register (SIU_EMPCR0)
  151. System configuration
  152. GPIO operation
  153. Internal multiplexing
  154. Lock detection
  155. Frequency modulation
  156. Miscellaneous Wakeup Control Register (ECSM_MWCR)
  157. Miscellaneous User-Defined Control Register (ECSM_MUDCR)
  158. ECC registers
  159. Memory map
  160. Internal boot mode
  161. BAM program operation
  162. Reset configuration half word (RCHW)
  163. Serial boot mode
  164. Booting from the External Bus Interface (EBI)
  165. Device-specific features
  166. External signals description
  167. Global registers
  168. Channel registers
  169. IP bus interface unit (BIU)
  170. Global clock prescaler submodule (GCP)
  171. REACM_RCHn — REACM Channel (n) Output Pin a, b and c
  172. REACM module configuration register (REACM_MCR)
  173. REACM Timer Configuration Register (REACM_TCR)
  174. REACM Threshold Router Register (REACM_THRR)
  175. REACM ADC Sensor Input Register (REACM_SINR)
  176. REACM Global Error Flag Register (REACM_GEFR)
  177. REACM Channel n Configuration Register (REACM_CHCRn)
  178. REACM Channel n Status Register (REACM_CHSRn)
  179. REACM Channel n Router Register (REACM_CHRRn)
  180. REACM Shared Timer Bank Registers (REACM_STBK)
  181. REACM Threshold Bank Register (REACM_THBK)
  182. REACM ADC result maximum limit check register (REACM_ADCMAX)
  183. REACM Modulation Minimum Pulse Width Register (REACM_MINPWD)
  184. REACM Modulation Control Word Bank Registers (REACM_MWBK)
  185. Modulation control words bank
  186. Shared timer bank
  187. Hold-off timer bank
  188. Threshold bank and comparator
  189. ADC interface
  190. Prescalers
  191. Modulation Modes
  192. Limitations on the modulation process
  193. Monitored modulation
  194. DMA support
  195. Reset overview
  196. Interrupt sources
  197. Advancing modulation phase on a threshold level
  198. Controlling the loop function
  199. Banked mode
  200. Memory map/register definition
  201. System configuration registers
  202. Time base registers
  203. Engine related registers
  204. Channel registers layout
  205. Channel configuration and control registers
  206. Host interface
  207. Scheduler
  208. Parameter sharing and coherency
  209. Enhanced Channels
  210. Time Bases
  211. EAC – eTPU angle counter
  212. Microengine
  213. Microinstruction set
  214. Test and Development Support
  215. Reset options
  216. Programming hints and caveats
  217. Estimating worst-case latency
  218. Endianness
  219. Initialization code example
  220. Predefined channel mode summary
  221. MISC algorithm
  222. Availability of Analog Inputs
  223. Debug mode
  224. Stop mode
  225. EQADC Register Descriptions
  226. On-Chip ADC Registers
  227. Data Flow in EQADC
  228. Command/Result Queues
  229. EQADC Command FIFOs
  230. EQADC Result FIFOs
  231. On-Chip ADC Configuration and Control
  232. Internal/External Multiplexing
  233. EQADC Synchronous Serial Interface (SSI) Sub-Block
  234. EQADC Parallel Side Interface (PSI) Sub-Block
  235. Analog Sub-Block
  236. EQADC/DMAC Interface
  237. Sending immediate command setup example
  238. Modifying queues
  239. CQueue and RQueues usage
  240. ADC Result Calibration
  241. Integrator halt signal
  242. Decimation filter register descriptions
  243. Decimation Filter Memory Map for Parallel Side Interface
  244. PSI Register Description
  245. Output buffer description
  246. Bypass configuration description
  247. IIR and FIR filter
  248. Filter prefill control description
  249. Timestamp data transmission
  250. Soft-reset command description
  251. Interrupts requests description
  252. DMA requests description
  253. Freeze mode description
  254. Integrator
  255. Cascade mode description
  256. Filter example simulation
  257. Input data calculation
  258. Filter results
  259. Temperature formula
  260. Registers
  261. Calculating a CRC checksum
  262. Configuring the context
  263. Initializing the context seed value
  264. Reading the checksum
  265. CRC Configuration Register (CRC_CFG)
  266. CRC Input Register (CRC_INP)
  267. CRC Current Status Register (CRC_CSTAT)
  268. CRC Output Register (CRC_OUTP)
  269. Use cases and limitations
  270. DSPI configurations
  271. SPI configuration
  272. CSI configuration
  273. Memory map and register definition
  274. Start and stop of DSPI transfers
  275. Deserial serial interface (DSI) configuration
  276. Combined serial interface (CSI) configuration
  277. DSPI baud rate and clock delay generation
  278. Transfer formats
  279. Continuous serial communications clock
  280. Timed serial bus (TSB)
  281. Parity generation and check
  282. Interrupts/DMA requests
  283. Buffered SPI operation
  284. Continuous peripheral chip select
  285. Modified SPI transfer format
  286. DSPI connections to eTPU_A, eMIOS and SIU
  287. Power saving features
  288. Switching master and slave mode
  289. Delay settings
  290. Calculation of FIFO pointer addresses
  291. Baud rate and clock generation
  292. Baud rate tolerance
  293. SCI mode
  294. LIN mode
  295. Interrupts
  296. Application Information
  297. Signal descriptions
  298. Message buffer architecture
  299. Message buffer structure
  300. Rx FIFO structure
  301. Transmit process
  302. Receive process
  303. Matching process
  304. Data coherence
  305. Rx FIFO
  306. CAN protocol related features
  307. Modes of operation details
  308. Bus interface
  309. FlexCAN addressing and RAM size configurations
  310. Color coding
  311. Controller host interface clocking
  312. Oscillator clocking
  313. Message buffer types
  314. FlexRay memory area layout
  315. Physical message buffer description
  316. Individual message buffer functional description
  317. Individual message buffer search
  318. Individual message buffer reconfiguration
  319. Receive FIFOs
  320. Channel device modes
  321. External clock synchronization
  322. Sync frame ID and sync frame deviation tables
  323. MTS generation
  324. Key slot transmission
  325. Sync frame filtering
  326. Strobe signal support
  327. Timer support
  328. Slot status monitoring
  329. System bus access
  330. Interrupt support
  331. Lower bit rate support
  332. CHI lookup-table memory (CHI LRAM)
  333. Memory content error detection
  334. Memory error injection
  335. Initialization Sequence
  336. Shut down sequence
  337. Number of usable message buffers
  338. Protocol control command execution
  339. Message buffer search on simple message buffer configuration
  340. Module Configuration Register (MCR)
  341. Trimming Register (TRIMR)
  342. Status Register (SR)
  343. V internal voltage regulator
  344. V LVI
  345. V voltage regulator controller
  346. Soft-Start (for 1.2 V and 3.3 V regulators)
  347. Electrical characteristics
  348. Register definition
  349. JTAGC block instructions
  350. Boundary scan
  351. Parameter values
  352. IEEE 1149.1-2001 (JTAG) TAP
  353. Nexus JTAG port sharing
  354. Nexus reset control
  355. DTS device connections
  356. DTS register access
  357. DTS Startup Register (DTS_STARTUP)
  358. DTS Semaphore Register (DTS_SEMAPHORE)
  359. Example application
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MPC5644A
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