Power Management Controller (PMC)MPC5644A Microcontroller Reference Manual, Rev. 61638 Freescale Semiconductor35.2.1.1 VDDREGQuiet 5 V supply for the voltage regulator and LVI block. It must have an external decoupling capacitorof the order of 4.7 μF – 20 μF. Regulators and LVI can be turned off by grounding VDDREG. In this caseexternal regulation and low voltage control must be supplied.35.2.1.2 VDDEH1Power supply input (5 V or 3.3 V nominal), taken from one of the pad ring I/O segment which is near thevoltage regulator.35.2.1.3 VRC33When the internal 3.3 V voltage regulator is enabled, this pin must be connected to an external bypasscapacitor of 600 nF – 2 μF with low ESR (max 50 m). If the voltage regulator is not powered or theregulator is disabled (pin VDDREG to ground or shutdown bit PMC_SR[V33DIS] set to ‘1’), this pin mustbe connected to an external 3.3 V supply.35.2.1.4 VDDThis is the 1.2 V supply coming from the emitter of an external NPN ballast transistor, whose base currentis supplied by VRCCTL. If the internal voltage regulator controller is not powered (pin VDDREG tied toground) or the external ballast transistor is not present, the VDD pin must be connected to an external 1.2 Vpower supply.For maximum transient performance, the recommended bypass capacitor for each pin that supplies thedigital core is 2.2 μF – 6 μF with very low ESR (max 50 m). A ceramic capacitor is also desirable, with100 nF capacitance. Moreover, a 1 μF to 2 μF cap might be connected to the base of the external bipolar.35.2.1.5 VRCCTL1.2 V regulator output that drives the base of the external NPN transistor.35.3 Memory map/register definitionTable 35-2 shows the PMC memory map. The PMC memory map has three registers for configuring,monitoring, and trimming the LVI monitors.NOTEThe PMC base address (PMC_BASE) is 0xC3FB_C000. Register addressesin this chapter are given as offsets to PMC_BASE.
