Enhanced Direct Memory Access Controller (eDMA)MPC5644A Microcontroller Reference Manual, Rev. 6Freescale Semiconductor 179group-priority error and channel-priority error, or EDMA_ESR[GPE] and EDMA_ESR[CPE],respectively.For all error types other than group- or channel-priority errors, the channel number causing the error isrecorded in the EDMA_ESR. If the error source is not removed before the next activation of the problemchannel, the error is detected and recorded again.Channel-priority errors are identified within a group after that group has been selected as the active group.For example, all of the channel priorities in group 1 are unique, but some of the channel priorities in group0 are the same:1. The DMA is configured for fixed-group and fixed-channel arbitration modes.2. Group 1 is the highest priority and all channels are unique in that group.3. Group 0 is the next highest priority and has two channels with the same priority level.4. If group 1 has any service requests, those requests are executed.5. After all of group 1 requests have completed, group 0 becomes the next active group.6. If group 0 has a service request, then an undefined channel in group 0 is selected and achannel-priority error will occur.7. This repeats until the all of group 0 requests have been removed or a higher priority group 1 requestcomes in.In this sequence, for item 2, the DMA acknowledge lines assert only if the selected channel is requestingservice via the DMA peripheral request signal. If interrupts are enabled for all channels, the user receivesan error interrupt, but the channel number for the EDMA_ER and the error interrupt request line areundetermined because they reflect the undefined channel. A group-priority error is global and any requestin any group causes a group-priority error.If priority levels are not unique, the highest (channel/group) priority that has an active request is selected,but the lowest numbered (channel/group) with that priority is selected by arbitration and executed by theDMA engine. The hardware service request handshake signals, error interrupts, and error reporting areassociated with the selected channel.8.5.3 DMA request assignmentsThe assignments between the DMA requests from the modules to the channels of the eDMA are shown inTable 8-22. The source column is written in C language syntax. The syntax ismodule_instance.register[bit].Table 8-22. DMA request summary for eDMADMA request Channel Source DescriptioneQADC_FISR0_CFFF0 0 EQADC.FISR0[CFFF0] eQADC Command FIFO 0 Fill FlageQADC_FISR0_RFDF0 1 EQADC.FISR0[RFDF0] eQADC Receive FIFO 0 Drain FlageQADC_FISR1_CFFF1 2 EQADC.FISR1[CFFF1] eQADC Command FIFO 1 Fill FlageQADC_FISR1_RFDF1 3 EQADC.FISR1[RFDF1] eQADC Receive FIFO 1 Drain Flag
