FlexCAN ModuleMPC5644A Microcontroller Reference Manual, Rev. 61424 Freescale Semiconductor2. Read the ID field (optional – needed only if a mask was used)3. Read the Data field4. Read the Free Running Timer (optional – releases the internal lock)Upon reading the Control and Status word, if the BUSY bit is set in the Code field, then the CPU shoulddefer the access to the message buffer until this bit is negated. Reading the Free Running Timer is notmandatory. If not executed the message buffer remains locked, unless the CPU reads the C/S word ofanother message buffer. Note that only a single message buffer is locked at a time. The only mandatoryCPU read operation is the one on the Control and Status word to assure data coherency (see Section 32.5.6,Data coherence).The CPU should synchronize to frame reception by the status flag bit for the specific message buffer in thecorresponding IFRL or IFRH register and not by the Code field of that message buffer. Polling the Codefield does not work because once a frame was received and the CPU services the message buffer (byreading the C/S word followed by unlocking the message buffer), the Code field will not return to EMPTY.It will remain FULL, as explained in Table 32-5. If the CPU tries to workaround this behavior by writingto the C/S word to force an EMPTY code after reading the message buffer, the message buffer is actuallydeactivated from any currently ongoing matching process. As a result, a newly received frame matchingthe ID of that message buffer may be lost. In summary: never do polling by reading directly the C/Sword of the message buffers. Instead, read the corresponding IFRL or IFRH register.Note that the received ID field is always stored in the matching message buffer, thus the contents of the IDfield in a message buffer may change if the match was due to masking. Note also that FlexCAN doesreceive frames transmitted by itself if there exists an Rx matching message buffer, providedMCR[SRX_DIS] is not asserted. If MCR[SRX_DIS] is asserted, FlexCAN will not store framestransmitted by itself in any message buffer, even if it contains a matching message buffer, and no interruptflag or interrupt signal will be generated due to the frame reception.To be able to receive CAN frames through the FIFO, the CPU must enable and configure the FIFO duringFreeze Mode (see Section 32.5.7, Rx FIFO). Upon receiving the frames available interrupt from FIFO, theCPU should service the received frame using the following procedure:1. Read the Control and Status word (optional – needed only if a mask was used for IDE and RTRbits)2. Read the ID field (optional – needed only if a mask was used)3. Read the Data field4. Clear the frames available interrupt (mandatory – release the buffer and allow the CPU to read thenext FIFO entry)32.5.5 Matching processThe matching process is an algorithm executed by the MBM that scans the message buffer memorylooking for Rx message buffers programmed with the same ID as the one received from the CAN bus. Ifthe FIFO is enabled, the 8-entry ID table from FIFO is scanned first and then, if a match is not found withinthe FIFO table, the other message buffers are scanned. In the event that the FIFO is full, the matchingalgorithm will always look for a matching message buffer outside the FIFO region.
