Peripheral Bridge (PBRIDGE)MPC5644A Microcontroller Reference Manual, Rev. 6208 Freescale Semiconductor10.6.2 Register descriptions10.6.2.1 Master privilege control registers (MPCR)Each MPCR register contains one or more 4-bit fields, called MPCRn, as shown in Table 10-2. Each ofthese fields defines the access privilege level associated with bus master n in the platform as well asspecifies whether write accesses from this master are bufferable. The registers provide one field per busmaster. See the “Logical master IDs” section in the XBAR chapter for a list of master numbers and names.Each MPCRn field has the structure described in Figure 10-2 and Table 10-3.Figure 10-2. MPCRn field structure0 1 2 3R 0 MTR MTW MPLWReset 0 1 1 1Table 10-3. MPCRn field structure descriptionsSubfield DescriptionMTR Master Trusted for ReadsThis bit determines whether the master is trusted for read accesses.0 This master is not trusted for read accesses.1 This master is trusted for read accesses.MTW Master Trusted for WritesThis bit determines whether the master is trusted for write accesses.0 This master is not trusted for write accesses.1 This master is trusted for write accesses.MPL Master Privilege LevelThis bit determines how the privilege level of the master is determined.0 Accesses from this master are forced to user-mode.1 Accesses from this master are not forced to user-mode.Table 10-4. MPCR register fieldsRegister Master name Reset valueMPCR 0 z4 core (instruction + load/store) 0b0111, meaningMTR = 1MTW = 1MPL = 1MPCR 4 DMAMPCR 6 FlexRayMPCR 7 EBIMPCR 8 z4 core Nexus
