Deserial Serial Peripheral Interface (DSPI)MPC5644A Microcontroller Reference Manual, Rev. 61304 Freescale SemiconductorFigure 30-37. Peripheral chip select strobe timingThe delay between the assertion of the PCS signals and the assertion of PCSS is selected by fieldDSPI_CTAR[PCSSCK] based on the following formula:Eqn. 30-5At the end of the transfer the delay between PCSS negation and PCS negation is selected by fieldDSPI_CTAR[PASC] based on the following formula:Eqn. 30-6Table 30-37 shows an example of how to compute the tpcssck delay.Table 30-38 shows an example of how to compute the tpasc delay.The PCSS signal is not supported when Continuous Serial Communication SCK or TSB mode are enabled.30.9.6 Transfer formatsThe SPI serial communication is controlled by the Serial Communications Clock (SCK) signal and thePCS signals. The SCK signal provided by the master device synchronizes shifting and sampling of the dataon the SIN and SOUT pins. The PCS signals serve as enable signals for the slave devices.When the DSPI is the bus master, the CPOL and CPHA bits in the DSPI Clock and Transfer AttributesRegisters (DSPI_CTARx) select the polarity and phase of the serial clock, SCK. The polarity bit selectsthe idle state of the SCK. The clock phase bit selects if the data on SOUT is valid before or on the firstSCK edge.When the DSPI is the bus slave, CPOL and CPHA bits in the DSPI_CTAR0 (SPI) or DSPI_CTAR1 (DSI)select the polarity and phase of the serial clock. Even though the bus slave does not control the SCK signal,Table 30-37. Peripheral chip select strobe assert computation examplef sys PCSSCK Prescaler Delay before transfer100 MHz 0b11 7 70.0 nsTable 30-38. Peripheral chip select strobe negate computation examplef sys PASC Prescaler Delay after transfer100 MHz 0b11 7 70.0 nstPCSSCKPCSSPCSxtPASCt PCSSCK1f SYS---------- PCSSCK=t PASC1f SYS---------- PASC=
