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Configurable Enhanced Modular IO Subsystem (eMIOS200)MPC5644A Microcontroller Reference Manual, Rev. 6642 Freescale Semiconductor22.3 External signals descriptionEach channel has one external input and one external output signal. Depending on the chip integration, theinput and output signals can be connected to two separate pins, or to a single bidirectional pin. SeeChapter 3 Signal Description for details.22.4 Memory map/register definition22.4.1 Memory mapThe overall address map organization is shown in Table 22-2.NOTEWhenever an access to either an absent register, an absent channel or areserved address is performed, the eMIOS200 responds by asserting aTransfer Error signal from the slave bus (or STAC bus).Output Pulse Width and Frequency Modulation Buffered OPWFMB on page 22-674Output Pulse Width Modulation Buffered OPWMB on page 22-679Table 22-2. MPC5644A eMIOS memory mapOffset fromEMIOS_BASE(0xC3FA_0000)Register LocationGlobal registers0x0000 EMIOS_MCR—Module Configuration Register on page 22-6490x0004 EMIOS_GFR—Global FLAG Register on page 22-6510x0008 EMIOS_OUDR—Output Update Disable Register on page 22-6510x000C EMIOS_UCDIS—Channel Disable Register on page 22-6520x000C–0x001F ReservedChannel 0 registers0x0020 EMIOS_CADR[0]—Channel A Data Register on page 22-6530x0024 EMIOS_CBDR[0]—Channel B Data Register on page 22-6530x0028 EMIOS_CCNTR[0]—Channel Counter Register on page 22-6540x002C EMIOS_CCR[0]—Channel Control Register on page 22-6550x0030 EMIOS_CSR[0]—Channel Status Register on page 22-6590x0034 EMIOS_ALTA[0] 1—Alternate A Register on page 22-660Table 22-1. All available MPC5644A eMIOS channel configurations (continued)Description Name Location