3 . I ns t r uc ti on Se t3- 3 0 3API Mnemonic Operands Function ControllersES2/EX2 SS2 SA2SESX2107 LRC P LRC checksumTypeOPBit Devices Word devices Program StepsX Y M S K H KnX KnY KnM KnS T C D E F LRC, LRCP: 7 stepsS *n * * *D *PULSE 16-bit 32-bitES2/EX2 SS2 SA2SE SX2 ES2/EX2 SS2 SA2SE SX2 ES2/EX2 SS2 SA2SE SX2Operands:S: Starting device for ASCII mode checksum n: Data length for LRC operation (n = K1~K256)D: Starting device for storing the operation resultExplanations:1. n: n must be an even number. If n is out of range, an error will occur and the instruction will notbe executed. At this time, M1067 and M1068 = ON and error code H’0E1A will be recorded inD1067.2. 16-bit mode: When LRC instruction operates with M1161 = OFF, hexadecimal data starting fromS is divided into high byte and low byte and the checksum operation is operated on n number ofbytes. After this, operation result will be stored in both hi-byte and low byte of D.3. 8-bit mode: When LRC instruction operates with M1161 = ON, hexadecimal data starting from Sis divided into high byte (invalid) and low byte and the checksum operation is operated on nnumber of low bytes. After this, operation result will be stored in low bytes of D (Consecutive 2registers).4. Flag: M1161 8/16-bit mode
