40.4.1.2 Debug modeIn Debug mode, the timers will be frozen based on MCR[FRZ]. This is intended to aidsoftware development, allowing the developer to halt the processor, investigate thecurrent state of the system, for example, the timer values, and then continue theoperation.40.4.2 InterruptsAll the timers support interrupt generation. See the MCU specification for related vectoraddresses and priorities.Timer interrupts can be enabled by setting TCTRLn[TIE]. TFLGn[TIF] are set to 1 whena timeout occurs on the associated timer, and are cleared to 0 by writing a 1 to thecorresponding TFLGn[TIF].40.4.3 Chained timersWhen a timer has chain mode enabled, it will only count after the previous timer hasexpired. So if timer n-1 has counted down to 0, counter n will decrement the value byone. This allows to chain some of the timers together to form a longer timer. The firsttimer (timer 0) cannot be chained to any other timer.40.5 Initialization and application informationIn the example configuration:• The PIT clock has a frequency of 50 MHz.• Timer 1 creates an interrupt every 5.12 ms.• Timer 3 creates a trigger event every 30 ms.The PIT module must be activated by writing a 0 to MCR[MDIS].The 50 MHz clock frequency equates to a clock period of 20 ns. Timer 1 needs to triggerevery 5.12 ms/20 ns = 256,000 cycles and Timer 3 every 30 ms/20 ns = 1,500,000 cycles.The value for the LDVAL register trigger is calculated as:LDVAL trigger = (period / clock period) -1Chapter 40 Periodic Interrupt Timer (PIT)K22F Sub-Family Reference Manual, Rev. 4, 08/2016NXP Semiconductors 1037
