Section number Title Page24.7 Memory map and register definition.............................................................................................................................52824.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)........................................................... 52924.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................ 53124.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH)................................................................. 53124.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL).................................................................. 53224.7.5 Watchdog Window Register High (WDOG_WINH).................................................................................. 53224.7.6 Watchdog Window Register Low (WDOG_WINL)................................................................................... 53324.7.7 Watchdog Refresh register (WDOG_REFRESH)....................................................................................... 53324.7.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................53324.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH)................................................................. 53424.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL).................................................................. 53424.7.11 Watchdog Reset Count register (WDOG_RSTCNT).................................................................................. 53524.7.12 Watchdog Prescaler register (WDOG_PRESC).......................................................................................... 53524.8 Watchdog operation with 8-bit access.......................................................................................................................... 53524.8.1 General guideline......................................................................................................................................... 53524.8.2 Refresh and unlock operations with 8-bit access......................................................................................... 53624.9 Restrictions on watchdog operation..............................................................................................................................537Chapter 25Multipurpose Clock Generator (MCG)25.1 Introduction...................................................................................................................................................................53925.1.1 Features........................................................................................................................................................ 53925.1.2 Modes of Operation..................................................................................................................................... 54325.2 External Signal Description.......................................................................................................................................... 54325.3 Memory Map/Register Definition.................................................................................................................................54325.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................54425.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................54525.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................54625.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................54725.3.5 MCG Control 5 Register (MCG_C5)...........................................................................................................548K22F Sub-Family Reference Manual, Rev. 4, 08/2016NXP Semiconductors 19
