b. If the TDRE flag is set, or there is space in the transmit buffer, write the data tobe transmitted to (C3[T8]/D). A new transmission will not result until data existsin the transmit buffer.3. Repeat step 2 for each subsequent transmission.NoteDuring normal operation, S1[TDRE] is set when the shiftregister is loaded with the next data to be transmitted from thetransmit buffer and the number of datawords contained in thetransmit buffer is less than or equal to the value inTWFIFO[TXWATER]. This occurs 9/16ths of a bit time afterthe start of the stop bit of the previous frame.To separate messages with preambles with minimum idle line time, use this sequencebetween messages.1. Write the last dataword of the first message to C3[T8]/D.2. Wait for S1[TDRE] to go high with TWFIFO[TXWATER] = 0, indicating thetransfer of the last frame to the transmit shift register.3. Queue a preamble by clearing and then setting C2[TE].4. Write the first and subsequent datawords of the second message to C3[T8]/D.47.8.4 Overrun (OR) flag implicationsTo be flexible, the overrun flag (OR) operates slight differently depending on the modeof operation. There may be implications that need to be carefully considered. This sectionclarifies the behavior and the resulting implications. Regardless of mode, if a dataword isreceived while S1[OR] is set, S1[RDRF] and S1[IDLE] are blocked from asserting. IfS1[RDRF] or S1[IDLE] were previously asserted, they will remain asserted until cleared.47.8.4.1 Overrun operationThe assertion of S1[OR] indicates that a significant event has occurred. The assertionindicates that received data has been lost because there was a lack of room to store it inthe data buffer. Therefore, while S1[OR] is set, no further data is stored in the data bufferuntil S1[OR] is cleared. This ensures that the application will be able to handle theoverrun condition.Chapter 47 Universal Asynchronous Receiver/Transmitter (UART)K22F Sub-Family Reference Manual, Rev. 4, 08/2016NXP Semiconductors 1297
