45.4.2 Serial Peripheral Interface (SPI) configurationThe SPI configuration transfers data serially using a shift register and a selection ofprogrammable transfer attributes. The module is in SPI configuration when the DCONFfield in the MCR is 0b00. The SPI frames can be 32 bits long. The host CPU or a DMAcontroller transfers the SPI data from the external to the module RAM queues to a TXFIFO buffer. The received data is stored in entries in the RX FIFO buffer. The host CPUor the DMA controller transfers the received data from the RX FIFO to memory externalto the module. The operation of FIFO buffers is described in the following sections:• Transmit First In First Out (TX FIFO) buffering mechanism• Transmit First In First Out (TX FIFO) buffering mechanism• Receive First In First Out (RX FIFO) buffering mechanismThe interrupt and DMA request conditions are described in Interrupts/DMA requests.The SPI configuration supports two block-specific modes—Master mode and Slavemode.In Master mode the module initiates and controls the transfer according to thefields of the executing SPI Command. In Slave mode, the module responds only totransfers initiated by a bus master external to it and the SPI command field space isreserved.45.4.2.1 Master modeIn SPI Master mode, the module initiates the serial transfers by controlling the SCK andthe PCS signals. The executing SPI Command determines which CTARs will be used toset the transfer attributes and which PCS signals to assert. The command field alsocontains various bits that help with queue management and transfer protocol. See PUSHTX FIFO Register In Master Mode (SPI_PUSHR) for details on the SPI command fields.The data in the executing TX FIFO entry is loaded into the shift register and shifted outon the Serial Out (SOUT) pin. In SPI Master mode, each SPI frame to be transmitted hasa command associated with it, allowing for transfer attribute control on a frame by framebasis.45.4.2.2 Slave modeIn SPI Slave mode the module responds to transfers initiated by an SPI bus master. Itdoes not initiate transfers. Certain transfer attributes such as clock polarity, clock phase,and frame size must be set for successful communication with an SPI master. The SPISlave mode transfer attributes are set in the CTAR0. The data is shifted out with MSBfirst. Shifting out of LSB is not supported in this mode.Chapter 45 Serial Peripheral Interface (SPI)K22F Sub-Family Reference Manual, Rev. 4, 08/2016NXP Semiconductors 1153
