2. Hardware trace -- The DWT generates these packets, and the ITM emits them.3. Time stamping -- Timestamps are emitted relative to packets. The ITM contains a21-bit counter to generate the timestamp. The Cortex-M4 clock or the bitclock rate ofthe Serial Wire Viewer (SWV) output clocks the counter.4. Global system timestamping. Timestamps can optionally be generated using asystem-wide 48-bit count value.9.9 Core Trace ConnectivityThe ITM can route its data to the TPIU. (See the MCM (Miscellaneous Control Module)for controlling the routing to the TPIU.) This configuration enables the use of trace withlow cost tools while maintaining the compatibility with trace probes.9.10 TPIUThe TPIU acts as a bridge between the on-chip trace data from the Instrumentation TraceMacrocell (ITM) to a data stream, encapsulating IDs where required, that is then capturedby a Trace Port Analyzer (TPA). The TPIU is specially designed for low-cost debug.9.11 DWTThe DWT is a unit that performs the following debug functionality:• It contains four comparators that you can configure as a hardware watchpoint, a PCsampler event trigger, or a data address sampler event trigger. The first comparator,DWT_COMP0, can also compare against the clock cycle counter, CYCCNT. Thesecond comparator, DWT_COMP1, can also be used as a data comparator.• The DWT contains counters for:• Clock cycles (CYCCNT)• Folded instructions• Load store unit (LSU) operations• Sleep cycles• CPI (all instruction cycles except for the first cycle)• Interrupt overheadCore Trace ConnectivityK22F Sub-Family Reference Manual, Rev. 4, 08/2016210 NXP Semiconductors
