If the SAI transmitter or receiver is using an externally generated bit clock inasynchronous mode and that bit clock is generated by an SAI that is disabled in stopmode, then the transmitter or receiver should be disabled by software before entering stopmode. This issue does not apply when the transmitter or receiver is in a synchronousmode because all synchronous SAIs are enabled and disabled simultaneously.49.4.1.3 Bus clockThe bus clock is used by the control and configuration registers and to generatesynchronous interrupts and DMA requests.NOTEAlthough there is no specific minimum bus clock frequencyspecified, the bus clock frequency must be fast enough (relativeto the bit clock frequency) to ensure that the FIFOs can beserviced, without generating either a transmitter FIFO underrunor receiver FIFO overflow condition.49.4.2 SAI resetsThe SAI is asynchronously reset on system reset. The SAI has a software reset and aFIFO reset.49.4.2.1 Software resetThe SAI transmitter includes a software reset that resets all transmitter internal logic,including the bit clock generation, status flags, and FIFO pointers. It does not reset theconfiguration registers. The software reset remains asserted until cleared by software.The SAI receiver includes a software reset that resets all receiver internal logic, includingthe bit clock generation, status flags and FIFO pointers. It does not reset the configurationregisters. The software reset remains asserted until cleared by software.49.4.2.2 FIFO resetThe SAI transmitter includes a FIFO reset that synchronizes the FIFO write pointer to thesame value as the FIFO read pointer. This empties the FIFO contents and is to be usedafter TCSR[FEF] is set, and before the FIFO is re-initialized and TCSR[FEF] is cleared.The FIFO reset is asserted for one cycle only.Functional descriptionK22F Sub-Family Reference Manual, Rev. 4, 08/20161366 NXP Semiconductors
