If the intent of clearing the interrupt is such that it does not reassert, the interrupt serviceroutine must remove or clear the condition that originally caused the interrupt to assertprior to clearing the interrupt. There are multiple ways that this can be accomplished,including ensuring that an event that results in the wait timer resetting occurs, such as, thetransmission of another packet.47.8.10 Legacy and reverse compatibility considerationsRecent versions of the UART have added several new features. Whenever reasonablypossible, reverse compatibility was maintained. However, in some cases this was eithernot feasible or the behavior was deemed as not intended. This section describes severaldifferences to legacy operation that resulted from these recent enhancements. Ifapplication code from previous versions is used, it must be reviewed and modified to takethe following items into account. Depending on the application code, additional itemsthat are not listed here may also need to be considered.1. Various reserved registers and register bits are used, such as, MSFB and M10.2. This module now generates an error when invalid address spaces are used.3. While documentation indicated otherwise, in some cases it was possible forS1[IDLE] to assert even if S1[OR] was set.4. S1[OR] will be set only if the data buffer (FIFO) does not have sufficient room.Previously, the data buffer was always a fixed size of one and the S1[OR] flag wouldset so long as S1[RDRF] was set even if there was room in the data buffer. While theclearing mechanism has remained the same for S1[RDRF], keeping the OR flagassertion tied to the RDRF event rather than the data buffer being full would havegreatly reduced the usefulness of the buffer when its size is larger than one.5. Previously, when C2[RWU] was set (and WAKE = 0), the IDLE flag could reassertup to every bit period causing an interrupt and requiring the host processor to reassertC2[RWU]. This behavior has been modified. Now, when C2[RWU] is set (andWAKE = 0), at least one non-idle bit must be detected before an idle can be detected.Chapter 47 Universal Asynchronous Receiver/Transmitter (UART)K22F Sub-Family Reference Manual, Rev. 4, 08/2016NXP Semiconductors 1301
