Table 6-3. Flash Option Register Bit Definitions (continued)BitNumField Value Definition0 Low-power boot: OUTDIVx values in SIM_CLKDIV1 register are auto-configured atreset exit for higher divide values that produce lower power consumption at resetexit.• Core and system clock divider (OUTDIV1) and bus clock divider (OUTDIV2)are 0x7 (divide by 8)• Flash clock divider (OUTDIV4) and FlexBus clock divider (OUTDIV3) are 0xF(divide by 16)1 Normal boot: OUTDIVx values in SIM_CLKDIV1 register are auto-configured atreset exit for higher frequency values that produce faster operating frequencies atreset exit.• Core and system clock divider (OUTDIV1) and bus clock divider (OUTDIV2)are 0x0 (divide by 1)• Flash clock divider (OUTDIV4) and FlexBus clock divider (OUTDIV3) are 0x1(divide by 2)6.3.4 Boot sequenceAt power up, the on-chip regulator holds the system in a POR state until the input supplyis above the POR threshold. The system continues to be held in this static state until theinternally regulated supplies have reached a safe operating voltage as determined by theLVD. The Mode Controller reset logic then controls a sequence to exit reset.1. A system reset is held on internal logic, the RESET pin is driven out low, and theMCG is enabled in its default clocking mode.2. Required clocks are enabled (Core Clock, System Clock, Flash Clock, and any BusClocks that do not have clock gate control reset to disabled).3. The system reset on internal logic continues to be held, but the Flash Controller isreleased from reset and begins initialization operation while the Reset Control logiccontinues to drive the RESET pin out low.4. Early in reset sequencing the NVM option byte is read and stored to the FlashMemory module's FOPT register. If the LPBOOT is programmed for an alternateclock divider reset value, the system/core clock is switched to a slower clock speed.If the FAST_INIT bit is programmed clear, the Flash initialization switches to slowerclock resulting longer recovery times.5. When Flash Initialization completes, the RESET pin is released. If RESET continuesto be asserted (an indication of a slow rise time on the RESET pin or external drivein low), the system continues to be held in reset. Once the RESET pin is detectedhigh, the Core clock is enabled and the system is released from reset. EzPort mode isselected instead of the normal CPU execution if EZP_CS is low when the internalChapter 6 Reset and BootK22F Sub-Family Reference Manual, Rev. 4, 08/2016NXP Semiconductors 179
