During Compute Operation, the AIPS peripheral and external memory (FlexBus) space isdisabled and attempted accesses generate bus errors. The private peripheral bus (PPB)remains accessible during Compute Operation, including the MCM, System ControlSpace (SCS) (for NVIC and FPU), and SysTick. Although access to the GPIO registers issupported, the GPIO port data input registers do not return valid data since clocks aredisabled to the Port Control and Interrupt modules. By writing to the GPIO port dataoutput registers, it is possible to control those GPIO ports that are configured as outputpins.Compute Operation is controlled by the CPO register in the MCM, which is onlyaccessible to the CPU. Setting or clearing the CPOREQ bit in the MCM initiates entry orexit into Compute Operation. Compute Operation can also be configured to exitautomatically on detection of an interrupt, which is required in order to service mostinterrupts. Only the core system interrupts (exceptions, including NMI and SysTick) andany edge sensitive interrupts can be serviced without exiting Compute Operation.When entering Compute Operation, the CPOACK status bit indicates when entry hascompleted. When exiting Compute Operation in Run mode, the CPOACK status bitnegates immediately. When exiting Compute Operation in VLP Run mode, the exit isdelayed to allow the PMC to handle the change in power consumption. This delay meansthe CPOACK bit is polled to determine when the AIPS peripheral space can be accessedwithout generating a bus error.The DMA wakeup is also supported during Compute Operation and causes the CPOACKstatus bit to clear and the AIPS peripheral space to be accessible for the duration of theDMA wakeup. At the completion of the DMA wakeup, the device transitions back intoCompute Operation.7.2.4 Peripheral DozeSeveral peripherals support a Peripheral Doze mode, where a register bit can be used todisable the peripheral for the duration of a low-power mode. The flash memory can alsobe placed in a low-power state during Peripheral Doze via a register bit in the SIM.Peripheral Doze is defined to include all of the modes of operation listed below.• The CPU is in Wait mode.• The CPU is in Stop mode, including the entry sequence and for the duration of aDMA wakeup.• The CPU is in Compute Operation, including the entry sequence and for the durationof a DMA wakeup.Clocking modesK22F Sub-Family Reference Manual, Rev. 4, 08/2016184 NXP Semiconductors
