State Cycle DescriptionS0 All The read or write cycle is initiated. On the rising clock edge, FlexBus:• Places a valid address on FB_ADn• Asserts FB_TS/FB_ALE• Drives FB_R/W high for a read and low for a writeS1 All FlexBus:• Negates FB_TS/FB_ALE on the rising edge of FB_CLK• Asserts FB_CSn• Drives the data on FB_AD31– FB_ADX for writes• Tristates FB_AD31– FB_ADX for reads• Continues to drive the address on FB_AD pins that are unused for dataIf the external memory or perihperal asserts FB_TA, then the process moves to S2. If FB_TA is notasserted internally or externally, then S1 repeats.Read The external memory or peripheral drives the data before the next rising edge of FB_CLK (the risingedge that begins S2) with FB_TA asserted.S2 All For internal termination, FlexBus negates FB_CSn and the transfer is complete. For externaltermination, the external memory or peripheral negates FB_TA, and FlexBus negates FB_CSn afterthe rising edge of FB_CLK at the end of S2.Read FlexBus latches the data on the rising clock edge entering S2. The external memory or peripheralcan stop driving the data after this edge or continue to drive the data until the end of S3 or throughany additional address hold cycles.S3 All FlexBus invalidates the address, data, and FB_R/W on the rising edge of FB_CLK at the beginningof S3, terminating the transfer.31.4.11 FlexBus Timing ExamplesNoteThe timing diagrams throughout this section use signal namesthat may not be included on your particular device. Ignore theseextraneous signals.NoteThroughout this section:• FB_D[X] indicates a 32-, 16-, or 8-bit wide data bus• FB_A[Y] indicates an address bus that can be 32, 24, or 16bits wide.31.4.11.1 Basic Read Bus CycleDuring a read cycle, the MCU receives data from memory or a peripheral device. Thefollowing figure shows a read cycle flowchart.Chapter 31 External Bus Interface (FlexBus)K22F Sub-Family Reference Manual, Rev. 4, 08/2016NXP Semiconductors 709
