Table 3-7. AWIC Partial Stop, Stop and VLPS Wake-up Sources (continued)Wake-up source DescriptionCMPx Since no system clocks are available, functionality is limited, trigger mode provides wakeupfunctionality with periodic samplingI2C Address match wakeupUART Active edge on RXDLPUART Functional when using clock source which is active in Stop and VLPS modesUSB FS/LS Controller WakeupLPTMR Functional when using clock source which is active in Stop and VLPS modesRTC Functional in Stop/VLPS modesI2S (SAI) Functional when using an external bit clock or external master clockNMI Non-maskable interrupt3.2.4 FPU ConfigurationThis section summarizes how the module has been configured in the chip. For acomprehensive description of the module itself, see the module’s dedicated chapter.FPUTransfersARM Cortex M4Core PPBFigure 3-4. FPU configurationTable 3-8. Reference links to related informationTopic Related module ReferenceFull description FPU ARM Cortex-M4 Technical Reference ManualSystem memory map System memory mapClocking Clock DistributionPower Management Power ManagementTransfersPrivate Peripheral Bus(PPB)ARM Cortex M4 core ARM Cortex-M4 coreCore modulesK22F Sub-Family Reference Manual, Rev. 4, 08/201666 NXP Semiconductors
