10.4.3 Clock ModulesTable 10-7. OSC Signal DescriptionsChip signal name Module signalnameDescription I/OEXTAL0 EXTAL External clock/Oscillator input IXTAL0 XTAL Oscillator output OTable 10-8. RTC OSC Signal DescriptionsChip signal name Module signalnameDescription I/OEXTAL32 EXTAL32 32.768 kHz oscillator input IXTAL32 XTAL32 32.768 kHz oscillator output O10.4.4 Memories and Memory InterfacesTable 10-9. EzPort Signal DescriptionsChip signal name Module signalnameDescription I/OEZP_CLK EZP_CK EzPort Clock InputEZP_CS EZP_CS EzPort Chip Select InputEZP_DI EZP_D EzPort Serial Data In InputEZP_DO EZP_Q EzPort Serial Data Out OutputTable 10-10. FlexBus Signal DescriptionsChip signal name Module signalnameDescription I/OCLKOUT FB_CLK FlexBus Clock Output OFB_AD[31:0] 1 FB_AD31 - FB_AD0 This is the address and data bus, FB_AD.The number of byte lanes carrying the data is determined by theport size associated with the matching chip-select.The full 32-bit address is driven on the first clock of a bus cycle(address phase). After the first clock, the data is driven on the bus(data phase). During the data phase, the address is driven on thepins not used for data. For example, in 16-bit mode, the loweraddress is driven on FB_AD15–FB_AD0, and in 8-bit mode, thelower address is driven on FB_AD23–FB_AD0.I/OTable continues on the next page...Module Signal Description TablesK22F Sub-Family Reference Manual, Rev. 4, 08/2016230 NXP Semiconductors
