45.4.2.5.1 Filling the RX FIFOThe RX FIFO is filled with the received SPI data from the shift register. While the RXFIFO is not full, SPI frames from the shift register are transferred to the RX FIFO. Everytime an SPI frame is transferred to the RX FIFO, the RX FIFO Counter is incremented byone.If the RX FIFO and shift register are full and a transfer is initiated, the RFOF bit in theSR is set indicating an overflow condition. Depending on the state of the ROOE bit in theMCR, the data from the transfer that generated the overflow is either ignored or shifted into the shift register. If the ROOE bit is set, the incoming data is shifted in to the shiftregister. If the ROOE bit is cleared, the incoming data is ignored.45.4.2.5.2 Draining the RX FIFOHost CPU or a DMA can remove (pop) entries from the RX FIFO by reading the modulePOP RX FIFO Register (POPR). A read of the POPR decrements the RX FIFO Counterby one. Attempts to pop data from an empty RX FIFO are ignored and the RX FIFOCounter remains unchanged. The data, read from the empty RX FIFO, is undetermined.When the RX FIFO is not empty, the RX FIFO Drain Flag (RFDF) in the SR is set. TheRFDF bit is cleared when the RX_FIFO is empty and the DMA controller indicates that aread from POPR is complete or by writing a 1 to it.45.4.3 Module baud rate and clock delay generationThe SCK frequency and the delay values for serial transfer are generated by dividing thesystem clock frequency by a prescaler and a scaler with the option for doubling the baudrate. The following figure shows conceptually how the SCK signal is generated.System ClockPrescaler1Scaler1+DBR SCKFigure 45-4. Communications clock prescalers and scalersFunctional descriptionK22F Sub-Family Reference Manual, Rev. 4, 08/20161156 NXP Semiconductors
