25.4.3.1 MCG Internal Reference ClockThe MCG Internal Reference Clock (MCGIRCLK) provides a clock source for other on-chip peripherals and is enabled when C1[IRCLKEN]=1. When enabled, MCGIRCLK isdriven by either the fast internal reference clock (4 MHz IRC which can be divided downby the FRDIV factors) or the slow internal reference clock (32 kHz IRC). The IRCSclock frequency can be re-targeted by trimming the period of its IRCS selected internalreference clock. This can be done by writing a new trim value to theC3[SCTRIM]:C4[SCFTRIM] bits when the slow IRC clock is selected or by writing anew trim value to C4[FCTRIM]:C2[FCFTRIM] when the fast IRC clock is selected. Theinternal reference clock period is proportional to the trim value written.C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) and C4[FCTRIM]:C2[FCFTRIM] (ifC2[IRCS]=1) bits affect the MCGOUTCLK frequency if the MCG is in FBI or BLPImodes. C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) bits also affect theMCGOUTCLK frequency if the MCG is in FEI mode.Additionally, this clock can be enabled in Stop mode by setting C1[IRCLKEN] andC1[IREFSTEN], otherwise this clock is disabled in Stop mode.25.4.4 External Reference ClockThe MCG module can support an external reference clock in all modes. See the devicedatasheet for external reference frequency range. When C1[IREFS] is set, the externalreference clock will not be used by the FLL or PLL. In these modes, the frequency can beequal to the maximum frequency the chip-level timing specifications will support.If any of the CME bits are asserted the slow internal reference clock is enabled alongwith the enabled external clock monitor. For the case when C6[CME0]=1, a loss of clockis detected if the OSC0 external reference falls below a minimum frequency (floc_high orfloc_low depending on C2[RANGE0]). For the case when C8[CME1]=1, a loss of clock isdetected if the RTC external reference falls below a minimum frequency (floc_low).NOTEAll clock monitors must be disabled before entering these low-power modes: Stop, VLPS, VLPR, VLPW, LLS, and VLLSx.On detecting a loss-of-clock event, the MCU generates a system reset if the respectiveLOCRE bit is set. Otherwise the MCG sets the respective LOCS bit and the MCGgenerates a LOCS interrupt request. In the case where a OSC loss of clock is detected, thePLL LOCK status bit is cleared.Functional descriptionK22F Sub-Family Reference Manual, Rev. 4, 08/2016562 NXP Semiconductors
