NOTEIn Stop mode, the I2C module supports slave receive modeonly. To avoid I2C bus conflicts during wakeup from Stopmode, software must ensure the following before entering Stopmode:• I2C data transfers have completed.• The I2C module is in slave receive mode (C1[MST]=0,C1[TX]=0).NOTEDuring the wake-up process, if an external master continues tosend data to the slave, the baud rate under Stop mode must beless than 50 kbit/s. To avoid the slower baud rate under Stopmode, the master can add a short delay in firmware to wait untilthe wake-up process is complete and then send data.NOTEWake-up caused by an address match is not supported forSMBus mode.NOTEAfter I2C address matching wake-up, the master must wait atime long enough for the slave ISR to finish running and resendstart or repeat start signals.For the SRW bit to function properly, it only supports Address+Write to wake up by I2C address matching. Before enteringthe next low power mode, Address+Write must be sent tochange the SRW status.46.4.9 DMA supportIf the DMAEN bit is cleared and the IICIE bit is set, an interrupt condition generates aninterrupt request.If the DMAEN bit is set and the IICIE bit is set, an interrupt condition generates a DMArequest instead. DMA requests are generated by the transfer complete flag (TCF).If the DMAEN bit is set, only the TCF initiates a DMA request. All other events generateCPU interrupts.Functional descriptionK22F Sub-Family Reference Manual, Rev. 4, 08/20161210 NXP Semiconductors
