NOTEBefore the last byte of master receive mode, TXAK must be setto send a NACK after the last byte's transfer. Therefore, theDMA must be disabled before the last byte's transfer.NOTEIn 10-bit address mode transmission, the addresses to sendoccupy 2–3 bytes. During this transfer period, the DMA mustbe disabled because the C1 register is written to send a repeatstart or to change the transfer direction.46.5 Initialization/application informationModule Initialization (Slave)1. Write: Control Register 2• to enable or disable general call• to select 10-bit or 7-bit addressing mode2. Write: Address Register 1 to set the slave address3. Write: Control Register 1 to enable the I2C module and interrupts4. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data5. Initialize RAM variables used to achieve the routine shown in the following figureModule Initialization (Master)1. Write: Frequency Divider register to set the I2C baud rate (see example indescription of ICR)2. Write: Control Register 1 to enable the I2C module and interrupts3. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data4. Initialize RAM variables used to achieve the routine shown in the following figure5. Write: Control Register 1 to enable TX6. Write: Control Register 1 to enable MST (master mode)7. Write: Data register with the address of the target slave (the LSB of this bytedetermines whether the communication is master receive or transmit)The routine shown in the following figure encompasses both master and slave I2Coperations. For slave operation, an incoming I2C message that contains the properaddress begins I2C communication. For master operation, communication must beChapter 46 Inter-Integrated Circuit (I2C)K22F Sub-Family Reference Manual, Rev. 4, 08/2016NXP Semiconductors 1211
